Abstract: An embodiment of the present invention is a printing apparatus, comprising: a carriage on which a printing head is mounted and that can move reciprocally in a first direction; a motor configured to generate driving force; a driving shaft extending in the first direction and driven to rotate by the driving force; a plurality of driving units driven by the driving force transmitted through the driving shaft; a switching unit configured to switch a transmission destination of the driving force in the plurality of driving units in conjunction with the driving shaft; and a contact unit configured to rotate around a rotatably supporting unit so as to be in a contact position in which contact with the carriage is made or a non-contact position in which the contact with the carriage is not made and to move with the carriage in the contact position.

Abstract: Here is provided a method of producing a starch gel-containing food, the method comprising the steps of: treating starch granules with an enzyme at a temperature of about 10° C. or higher and about 70° C. or lower to obtain an enzyme-treated starch; mixing a food material, the enzyme-treated starch and water to obtain a mixture; heating the mixture thereby gelatinizing the enzyme-treated starch in the mixture; and cooling the mixture containing the gelatinized enzyme-treated starch thereby gelling the starch to obtain a starch gel-containing food, wherein the enzyme is selected from the group consisting of amyloglucosidase, isoamylase, ?-glucosidase, ?-amylase having a characteristic capable of improving a gel forming ability of a starch, and cyclodextrin glucanotransferase.

Abstract: A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments.

Abstract: Here is provided a method of producing a starch gel-containing food, the method comprising the steps of: treating starch granules with an enzyme at a temperature of about 10° C. or higher and about 70° C. or lower to obtain an enzyme-treated starch; mixing a food material, the enzyme-treated starch and water to obtain a mixture; heating the mixture thereby gelatinizing the enzyme-treated starch in the mixture; and cooling the mixture containing the gelatinized enzyme-treated starch thereby gelling the starch to obtain a starch gel-containing food, wherein the enzyme is selected from the group consisting of amyloglucosidase, isoamylase, ?-glucosidase, ?-amylase having a characteristic capable of improving a gel forming ability of a starch, and cyclodextrin glucanotransferase.

Abstract: Here is provided a method of producing a starch gel-containing food, the method comprising the steps of: treating starch granules with an enzyme at a temperature of about 10° C. or higher and about 70° C. or lower to obtain an enzyme-treated starch; mixing a food material, the enzyme-treated starch and water to obtain a mixture; heating the mixture thereby gelatinizing the enzyme-treated starch in the mixture; and cooling the mixture containing the gelatinized enzyme-treated starch thereby gelling the starch to obtain a starch gel-containing food, wherein the enzyme is selected from the group consisting of amyloglucosidase, isoamylase, ?-glucosidase, ?-amylase having a characteristic capable of improving a gel forming ability of a starch, and cyclodextrin glucanotransferase.

Abstract: Here is provided a method of producing a starch gel-containing food, the method comprising the steps of: treating starch granules with an enzyme at a temperature of about 10° C. or higher and about 70° C. or lower to obtain an enzyme-treated starch; mixing a food material, the enzyme-treated starch and water to obtain a mixture; heating the mixture thereby gelatinizing the enzyme-treated starch in the mixture; and cooling the mixture containing the gelatinized enzyme-treated starch thereby gelling the starch to obtain a starch gel-containing food, wherein the enzyme is selected from the group consisting of amyloglucosidase, isoamylase, ?-glucosidase, ?-amylase having a characteristic capable of improving a gel forming ability of a starch, and cyclodextrin glucanotransferase.

Abstract: The present invention relates to integrated circuit (IC) tags. The IC tag (40) placed on sheet products handled in batch units after production, and used to manage the sheet products. The IC tag includes an IC tag main body (41) having an IC chip and a radio antenna embedded therein, and a plate (42) with a flat portion (42a) in which the IC tag main body (41) is installed. The plate (42) has at its one end a protrusion (42b) extending from the flat portion (42a). This makes it possible to attach and detach the IC tag to and from the inner side of the paper tube.

Abstract: In projecting radioactive rays for sanitizing food or the like, an irradiating condition which attains a uniform dose of radioactive rays for the entire objects to be exposed is automatically determined. An X-ray CT unit 6 captures a sectional image of an object to be exposed 2, and an irradiating condition determining section 8 acquires the density distribution of the object to be exposed 2 based on the captured sectional image. The irradiating condition determining section 8 then searches for a particular irradiating condition under which the dose distribution of the radioactive rays in the object to be exposed 2 falls within a predetermined range. An irradiation controlling section 16 controls a radioactive ray irradiating unit 14 based on the irradiating condition, and projects radioactive rays to the object to be exposed 2 in accordance with the irradiation condition when the object is transported to the radioactive ray irradiating unit 14 by a belt conveyor.

Abstract: A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Abstract: A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Abstract: A hot melt colored ink comprising: a coloring component being at least one selected from the group consisting of carbon black, an inorganic pigment, an organic pigment, a dye and an inorganic extender pigment; phytosterol and/or a derivative thereof in an amount of 0.1 to 90% by weight of the hot melt colored ink; and optionally a thermoplastic resin in an amount of 1 to 80% by weight of the hot melt colored ink. According to the hot melt colored ink of the present invention, various disadvantages found in conventional hot melt colored ink, such as grime, patchy, unsharpness and stain of transferred print (transferred image) does not occur and a print evenness and a performance (a quality and resolving power of transferred recording image) of transferred print on a transferable recording material (transferable recording paper etc.) are sufficient.

Abstract: A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Abstract: A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: A semiconductor integrated circuit device with a copy-preventive function comprises a memory for storing data to be used by users, an input unit for performing various logical operations on at least one input information fed externally and accessing the memory, an output unit for performing various logical operations on the data at the time of supplying the data from the memory, a judging unit for comparing at least one of the state of the input information, the logical state of the input unit, the logical state of the output unit, and the state of data provided by the output unit with specific judgment information and indicating the result of comparison, and a control unit that when the result indicated by the judging unit reveals that the at least one of the states is consistent with a specific state, acts at least on the output unit so as to prevent data stored in the memory from being supplied normally.

Abstract: A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Abstract: An object of the present invention is to improve the output speed of a data signal output circuit having a latch circuit when the supply voltage is low. The data signal output circuit according to the present invention includes a latch circuit; an output circuit; a latch control circuit; an output control circuit; and a supply voltage decrease detection circuit. The latch circuit latches and holds a data signal according to a latch signal output from the latch control circuit. By setting the latch signal to one of two logical states, the latch circuit changes to a through state directly outputting an input data signal. The output circuit changes between a state for outputting a data signal from the latch circuit and a high-impedance state according to an output control signal output from the output control circuit. The supply voltage decrease detection circuit detects whether or not the supply voltage is less than a pre-determined value.

Abstract: Semiconductor memory devices, such as, SRAM IC memory devices, include a shield structure for shielding load elements in the memory cells of the memory devices from electric fields generated by surrounding active or passive elements, such as, an underlying MOSFET or a voltage supplying interconnect, to prevent deterioration of the operational resistance values and characteristics of the load elements. In the case of resistance elements utilized as load elements, a partial shield structure, i.e., a shield layer, at a constant voltage or zero volts, spatially underlying only a portion of the length of the resistance element is adequate to substantially remove the effect of such electric fields. In the case of TFT channel devices having channel offset regions utilized as load elements, a shield structure, i.e., a shield layer spatially underlying the TFT channel offset region is adequate to substantially remove the effect of such electric fields.

Abstract: An integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.