Patents by Inventor Masakazu Sugiura

Masakazu Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220236232
    Abstract: An ultrasonic inspection device is an device for ultrasonically inspecting a rotor disc. The ultrasonic inspection device includes: an inspecting portion that has an ultrasonic probe for transmitting an ultrasonic wave to a disc surface of the rotor disc; a first magnet that movably holds the ultrasonic probe relative to the disc surface of the rotor disc; a drive wheel that causes the ultrasonic probe to move in a direction that intersects a radial direction of the rotor disc; a steering wheel that adjusts a moving direction of the drive wheel; a stroke sensor that detects the radial position of the ultrasonic probe being held relative to the disc surface; and a control device that controls the steering wheel on the basis of information detected by the stroke sensor such that the radial position of the ultrasonic probe falls within a predetermined range.
    Type: Application
    Filed: May 18, 2020
    Publication date: July 28, 2022
    Applicant: Mitsubishi Power, Ltd.
    Inventors: Masakazu Kamibayashi, Atsushi Sugiura, Takuro Masuda
  • Patent number: 11275399
    Abstract: There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 15, 2022
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Fumihiko Maetani
  • Patent number: 10831219
    Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 10, 2020
    Assignee: ABLIC INC.
    Inventors: Tsutomu Tomioka, Tadakatsu Kuroda, Masakazu Sugiura
  • Patent number: 10637344
    Abstract: A source-grounded amplifier circuit supplied with a signal of an error amplifier circuit, and an output transistor supplied with a control voltage of the source-grounded amplifier circuit are provided. The source-grounded amplifier circuit has, in a signal path, a current limiting circuit including a cascode circuit controlled by a voltage having a positive temperature coefficient. A voltage regulator capable of reducing a dropout voltage of an output voltage without exceeding a gate breakdown voltage of the output transistor is provided.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 28, 2020
    Assignee: ABLIC INC.
    Inventors: Tsutomu Tomioka, Masakazu Sugiura
  • Patent number: 10574200
    Abstract: Provided is a transconductance amplifier including a common-mode feedback circuit that does not affect an operation of the transconductance amplifier. The transconductance amplifier has a transconductance amplifier circuit configured to generate an output current based on an input voltage and a common-mode feedback circuit configured to determine a DC operating point of an output of the transconductance amplifier circuit. The common-mode feedback circuit has a plurality of level shift circuits configured to shift levels of input voltages to output the voltages, and are connected to control terminals of a plurality of transistors.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 25, 2020
    Assignee: ABLIC INC.
    Inventor: Masakazu Sugiura
  • Patent number: 10505500
    Abstract: Provided is a differential amplification device reduced in DC offset voltage. The amplification device amplifies an input signal, and includes a chopper switch circuit which switches the polarity of the input signal between a normal phase and a reverse phase and outputs the input signal, a V-I conversion circuit which is connected to the chopper switch circuit, a capacitance circuit which is connected to the V-I conversion circuit to store electric charges supplied from the V-I conversion circuit, and an amplification circuit which is connected to the V-I conversion circuit to switch the polarity of an input signal between the normal phase and the reverse phase and amplify the input signal.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 10, 2019
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Toshiyuki Tsuzaki, Yuji Shiine, Manabu Fujimura
  • Patent number: 10503197
    Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 10, 2019
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Atsushi Igarashi, Nao Otsuka
  • Publication number: 20190302816
    Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.
    Type: Application
    Filed: February 28, 2019
    Publication date: October 3, 2019
    Inventors: Tsutomu TOMIOKA, Tadakatsu Kuroda, Masakazu Sugiura
  • Patent number: 10355675
    Abstract: To provide an input circuit which avoids power supply voltage dependency of a threshold of the input circuit when an output signal is transited. There is provided an input circuit equipped with an input transistor and a current source connected in series between a first power supply and a second power supply. The input circuit is configured in such a manner that an input signal is inputted to a gate of the input transistor and a signal of a connection point between the input transistor and the current source is outputted as an output signal, and a current value of the current source is changed based on the output signal.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 16, 2019
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Tsutomu Tomioka
  • Patent number: 10348305
    Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 9, 2019
    Assignee: ABLIC INC.
    Inventors: Hideyuki Sawai, Masakazu Sugiura
  • Publication number: 20190187739
    Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Inventors: Masakazu SUGIURA, Atsushi IGARASHI, Nao OTSUKA
  • Publication number: 20190115821
    Abstract: A source-grounded amplifier circuit supplied with a signal of an error amplifier circuit, and an output transistor supplied with a control voltage of the source-grounded amplifier circuit are provided. The source-grounded amplifier circuit has, in a signal path, a current limiting circuit including a cascode circuit controlled by a voltage having a positive temperature coefficient. A voltage regulator capable of reducing a dropout voltage of an output voltage without exceeding a gate breakdown voltage of the output transistor is provided.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 18, 2019
    Inventors: Tsutomu TOMIOKA, Masakazu SUGIURA
  • Publication number: 20180348807
    Abstract: There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 6, 2018
    Inventors: Masakazu SUGIURA, Fumihiko MAETANI
  • Patent number: 10148238
    Abstract: Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 4, 2018
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Toshiyuki Tsuzaki, Yuji Shiine, Manabu Fujimura
  • Publication number: 20180287567
    Abstract: Provided is a differential amplification device reduced in DC offset voltage. The amplification device amplifies an input signal, and includes a chopper switch circuit which switches the polarity of the input signal between a normal phase and a reverse phase and outputs the input signal, a V-I conversion circuit which is connected to the chopper switch circuit, a capacitance circuit which is connected to the V-I conversion circuit to store electric charges supplied from the V-I conversion circuit, and an amplification circuit which is connected to the V-I conversion circuit to switch the polarity of an input signal between the normal phase and the reverse phase and amplify the input signal.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Inventors: Masakazu SUGIURA, Toshiyuki TSUZAKI, Yuji SHIINE, Manabu FUJIMURA
  • Publication number: 20180287576
    Abstract: Provided is a transconductance amplifier including a common-mode feedback circuit that does not affect an operation of the transconductance amplifier. The transconductance amplifier has a transconductance amplifier circuit configured to generate an output current based on an input voltage and a common-mode feedback circuit configured to determine a DC operating point of an output of the transconductance amplifier circuit. The common-mode feedback circuit has a plurality of level shift circuits configured to shift levels of input voltages to output the voltages, and are connected to control terminals of a plurality of transistors.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 4, 2018
    Inventor: Masakazu SUGIURA
  • Publication number: 20180278221
    Abstract: To perform a rail-to-rail input operation, provided is a differential amplifier circuit including a first differential input pair and a second differential input pair which has a threshold value different from that of the first differential input pair. Both the differential input pairs do not operate at the same time. A transistor is connected between the first differential input pair and a current source to achieve a configuration in which the first differential input pair and the second differential input pair do not operate at the same time.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 27, 2018
    Inventors: Toshiyuki TSUZAKI, Masakazu SUGIURA
  • Publication number: 20180234087
    Abstract: Provided is a signal selection circuit including a control circuit capable of generating a drive signal having a fast rise/fall time. A positive feedback circuit is provided to the control circuit, which generates the drive signal for controlling a plurality of switches configured to switch an input signal to provide the signal to an output terminal.
    Type: Application
    Filed: November 29, 2017
    Publication date: August 16, 2018
    Inventors: Masakazu SUGIURA, Hideyuki SAWAI
  • Publication number: 20180205378
    Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.
    Type: Application
    Filed: November 29, 2017
    Publication date: July 19, 2018
    Inventors: Hideyuki SAWAI, Masakazu SUGIURA
  • Patent number: 9983068
    Abstract: Provided is an overheat detection circuit that is capable of quickly outputting an overheated state detection signal in an overheated state without outputting an unintended erroneous output caused by disturbance noise, such as momentary voltage fluctuations in the power supply. The overheat detection circuit includes: a temperature sensor; a comparison section; and a disturbance noise removal section configured to output an overheated state detection signal to an output section after a predetermined delay time has elapsed. The delay time is reduced in proportion to temperature.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 29, 2018
    Assignee: ABLIC INC.
    Inventors: Masakazu Sugiura, Hideyuki Sawai