Patents by Inventor Masaki Momodomi

Masaki Momodomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4799193
    Abstract: A semiconductor memory device having at least one memory cell array block with a plurality of memory cells formed at the surface of a semiconductor substrate. Each memory cell includes a transistor and memory capacitor. The device further has a plurality of word lines for addressing the memory cells, a plurality of bit lines for reading from and writing to the memory capacitors, at least one cell plate formed on the semiconductor substrate, the cell plate forming a common electrode of the memory capacitors, a cell plate voltage generator for supplying a voltage of a level between the supply voltage and the ground voltage to the cell plate, and a control circuit for controlling the output impedance of the cell plate voltage generating unit.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: January 17, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Horiguchi, Yasuo Itoh, Mitsugi Ogura, Masaki Momodomi
  • Patent number: 4751676
    Abstract: A semiconductor integrated circuit, comprises a semiconductor integrated circuit chip; a standard voltage generating means for generating standard voltage other than a supply voltage and a ground voltage, at least one, standard voltage wire for supplying the standard voltage to at least one circuit of said semiconductor integrated circuit chip; at least one first capacitor extending along the standard voltage wire, the first capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the supply voltage; and at least one second capacitor extending along the standard voltage wire, the second capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the ground voltage.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: June 14, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaki Momodomi
  • Patent number: 4697101
    Abstract: A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.
    Type: Grant
    Filed: August 29, 1984
    Date of Patent: September 29, 1987
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Micro-Computer Engineering Corp., Tosbac Computer System Co., Ltd.
    Inventors: Hiroshi Iwahashi, Masamichi Asano, Masaki Momodomi, Hidenobu Minagawa, Kazuto Suzuki, Akira Narita
  • Patent number: 4630088
    Abstract: A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the upper surface of each projection, a drain region of the second conductivity type formed in a bottom portion of each projection, a channel region of the first conductivity type sandwiched between the source and drain regions, a gate insulating film formed on a side wall of each projection between the source and drain regions, a gate electrode formed on the gate insulating film, a first insulating film formed on the source region, and a first electrode of the MOS capacitor formed on the first insulating film. The MOSFET is constituted by the source, drain and channel regions, the gate insulating film and the gate electrode.
    Type: Grant
    Filed: April 3, 1985
    Date of Patent: December 16, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsugi Ogura, Masaki Momodomi
  • Patent number: 4630087
    Abstract: In a nonvolatile semiconductor memory device having a matrix of electrically erasable and programmable memory cells each of which has a floating gate, an erase gate, and two control gates, a relationship among the potentials selectively applied to the floating gate, the erase gate, and the two control gates is preset to decrease changes in the threshold level of the half-selected memory cells, thereby achieving high reliability. In the writing mode, a voltage of +25 V is applied to the selected row and column control lines, a first low voltage of 0 V is applied to the remaining row and column control lines, and a second low voltage of +5 V is applied to a source control line. In the erasing mode, a low voltage of 0 V is applied to the selected row and column control lines, a first high voltage of +25 V is applied to the remaining row and column control lines, and a second high voltage of +20 V is applied to the source control line.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: December 16, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaki Momodomi