Patents by Inventor Masaki Murase
Masaki Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170069666Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.Type: ApplicationFiled: November 16, 2016Publication date: March 9, 2017Applicant: Japan Display Inc.Inventors: Gen KOIDE, Masaki MURASE, Nobuyuki ISHIGE
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Patent number: 9536910Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.Type: GrantFiled: March 25, 2016Date of Patent: January 3, 2017Assignee: Japan Display Inc.Inventors: Gen Koide, Masaki Murase, Nobuyuki Ishige
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Publication number: 20160300863Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.Type: ApplicationFiled: March 25, 2016Publication date: October 13, 2016Applicant: Japan Display Inc.Inventors: Gen KOIDE, Masaki MURASE, Nobuyuki ISHIGE
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Patent number: 9460903Abstract: The same sample S is analyzed using an ion-trap (IT) mass spectrometer section 11 in which ions are captured in an ion trap before mass spectrometry and a time-of-flight (TOF) mass spectrometer section 12 in which ions generated from the sample are directly subjected to mass spectrometry. A mass spectrum creator 21 creates an IT mass spectrum and a TOF mass spectrum from the measured results. A glycopeptide detector 23 detects fragment ion peaks related to neutral loss of sugars from the IT mass spectrum as well as peaks corresponding to intact molecular ions from the TOF mass spectrum, and furthermore, detects peaks common to the two spectra as glycopeptide ions. A quantitative analyzer 24 determines relative quantities of glycoforms of the glycopeptide based on the TOF mass spectrum. A structural analyzer 25 analyzes the structure of the glycopeptide using the result of an MSn analysis of the sample S.Type: GrantFiled: November 25, 2014Date of Patent: October 4, 2016Assignee: SHIMADZU CORPORATIONInventor: Masaki Murase
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Patent number: 9230785Abstract: There are provided an ion trap mass spectrometer and an ion trap mass spectrometry method which can realize reduction of the number of times that a sample is ionized, and shortening of the measurement time. Ions corresponding to a plurality of peaks P11, P12 and P13 with the intensity or S/N ratio falling within a predetermined range L are detected as MS2 precursor ions based on the MS1 spectrum. A plurality of ions detected as the MS2 precursor ions are dissociated at a time in an ion trap and subjected to mass spectrometry to measure a MS2 spectrum.Type: GrantFiled: January 30, 2015Date of Patent: January 5, 2016Assignee: SHIMADZU CORPORATIONInventor: Masaki Murase
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Publication number: 20150311228Abstract: A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Mitsufumi Sogabe, Masaki Murase, Hiroshi Mizuhashi
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Publication number: 20150235830Abstract: There are provided an ion trap mass spectrometer and an ion trap mass spectrometry method which can realize reduction of the number of times that a sample is ionized, and shortening of the measurement time. Ions corresponding to a plurality of peaks P11, P12 and P13 with the intensity or S/N ratio falling within a predetermined range L are detected as MS2 precursor ions based on the MS1 spectrum. A plurality of ions detected as the MS2 precursor ions are dissociated at a time in an ion trap and subjected to mass spectrometry to measure a MS2 spectrum.Type: ApplicationFiled: January 30, 2015Publication date: August 20, 2015Applicant: SHIMADZU CORPORATIONInventor: Masaki MURASE
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Patent number: 9111808Abstract: A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.Type: GrantFiled: October 15, 2014Date of Patent: August 18, 2015Assignee: JAPAN DISPLAY INC.Inventors: Mitsufumi Sogabe, Masaki Murase, Hiroshi Mizuhashi
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Publication number: 20150144783Abstract: The same sample S is analyzed using an ion-trap (IT) mass spectrometer section 11 in which ions are captured in an ion trap before mass spectrometry and a time-of-flight (TOF) mass spectrometer section 12 in which ions generated from the sample are directly subjected to mass spectrometry. A mass spectrum creator 21 creates an IT mass spectrum and a TOF mass spectrum from the measured results. A glycopeptide detector 23 detects fragment ion peaks related to neutral loss of sugars from the IT mass spectrum as well as peaks corresponding to intact molecular ions from the TOF mass spectrum, and furthermore, detects peaks common to the two spectra as glycopeptide ions. A quantitative analyzer 24 determines relative quantities of glycoforms of the glycopeptide based on the TOF mass spectrum. A structural analyzer 25 analyzes the structure of the glycopeptide using the result of an MSn analysis of the sample S.Type: ApplicationFiled: November 25, 2014Publication date: May 28, 2015Applicant: SHIMADZU CORPORATIONInventor: Masaki MURASE
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Patent number: 8975575Abstract: A mass spectrometry using helium as cooling gas is performed to obtain a first mass spectrum (S1), and another mass spectrometry using argon, which is heavier than helium, as cooling gas is performed to obtain a second mass spectrum for the same sample (S2). Due to the difference between the two gases in terms of the effect of promoting dissociation of modifications, an ion peak originating from a target compound from which all the modifications have been dissociated will appear with a higher intensity on the second mass spectrum. The peak patterns of the two mass spectra are compared to locate the all-dissociated ion peak while excluding unnecessary peaks (S3). Based on that peak, the assignment of each peak is determined (S4).Type: GrantFiled: April 4, 2012Date of Patent: March 10, 2015Assignee: Shimadzu CorporationInventors: Sadanori Sekiya, Masaki Murase, Hidenori Takahashi, Kentaro Morimoto
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Publication number: 20150028339Abstract: A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.Type: ApplicationFiled: October 15, 2014Publication date: January 29, 2015Inventors: Mitsufumi Sogabe, Masaki Murase, Hiroshi Mizuhashi
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Patent number: 8884919Abstract: Disclosed herein is a semiconductor device including: one or a plurality of pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.Type: GrantFiled: April 18, 2012Date of Patent: November 11, 2014Assignee: Japan Display West Inc.Inventors: Mitsufumi Sogabe, Masaki Murase, Hiroshi Mizuhashi
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Publication number: 20140224973Abstract: A mass spectrometry using helium as cooling gas is performed to obtain a first mass spectrum (S1), and another mass spectrometry using argon, which is heavier than helium, as cooling gas is performed to obtain a second mass spectrum for the same sample (S2). Due to the difference between the two gases in terms of the effect of promoting dissociation of modifications, an ion peak originating from a target compound from which all the modifications have been dissociated will appear with a higher intensity on the second mass spectrum. The peak patterns of the two mass spectra are compared to locate the all-dissociated ion peak while excluding unnecessary peaks (S3). Based on that peak, the assignment of each peak is determined (S4).Type: ApplicationFiled: April 4, 2012Publication date: August 14, 2014Applicant: SHIMADZU CORPORATIONInventors: Sadanori Sekiya, Masaki Murase, Hidenori Takahashi, Kentaro Morimoto
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Patent number: 8477123Abstract: A display apparatus including: an effective pixel section having a plurality of pixel circuits arranged to form a matrix, each pixel circuit including a switching device through which pixel video data is written into the pixel circuit; a plurality of scan lines each provided for an individual one of rows of the pixel circuits arranged on the effective pixel section to control the conduction states of the switching devices; a plurality of capacitor lines each arranged for individual one of the rows connected to the pixel circuits; a plurality of signal lines each arranged for individual one of columns connected to the pixel circuits to propagate the pixel video data; a first driving circuit configured to selectively drive the scan lines and the capacitor lines; and a second driving circuit configured to drive the signal lines.Type: GrantFiled: August 22, 2008Date of Patent: July 2, 2013Assignee: Japan Display West, Inc.Inventors: Kazuhisa Tomohiro, Masaki Murase, Takayuki Nakanishi, Naoyuki Itakura, Yoshitoshi Kida
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Patent number: 8339387Abstract: A display device able to amplify the same input as a power supply voltage of IC by using low temperature polysilicon having high threshold voltage and large variation and an electronic apparatus using the same, including MCK use level shifters 171-1 and 171-2 of a type where a reset operation is periodically necessary, a logic circuit 173 for using a level shift horizontal synchronization signal Hsync to input reset pulses for the MCK level shifters 171-1 and 171-2 having a period of N horizontal periods shifted in phase by M horizontal periods (note, M<N) to the level shifters 171-1 and 171-2 and outputting the resultant signals, and a function of selecting the circuit not performing the reset operation among outputs of the L number of level shifters 171-1 and 171-2 for each M horizontal periods and outputting a level shift master clock LSMCK as a last output signal.Type: GrantFiled: January 19, 2007Date of Patent: December 25, 2012Assignee: Sony CorporationInventors: Masaki Murase, Daisuke Ito, Masaaki Tonogai, Yoshitoshi Kida, Yoshiharu Nakajima
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Publication number: 20120274612Abstract: Disclosed herein is a semiconductor device including: one or a plurality of pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.Type: ApplicationFiled: April 18, 2012Publication date: November 1, 2012Applicant: SONY CORPORATIONInventors: Mitsufumi Sogabe, Masaki Murase, Hiroshi Mizuhashi
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Patent number: 8159438Abstract: Liquid crystal display devices to suffer from low contrast at low temperatures because the frequency characteristics of the liquid crystal dielectric constant are degraded. An active matrix liquid crystal display device performs pre-charging in which a pre-charge signal Psig is written with a pre-charge switch before display signals are written to data lines of a display area with a dated driver. The pre-charge signal Psig is the gray-scale level as obtained when no voltage is applied to liquid crystal, such as a common voltage VCOM, thus increasing the contrast at low temperature.Type: GrantFiled: April 28, 2003Date of Patent: April 17, 2012Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Masaki Murase
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Patent number: 7961167Abstract: A display device and mobile terminal are provided. The display device can narrow the pitch, narrow the frame, and further reduce power consumption. The display device includes a display area; a vertical drive circuit; a first horizontal drive circuit converting input first and second digital image data to analog image signals, and supplying the same to a data line selected by the vertical drive circuit; and a second horizontal drive circuit converting input third digital image data to an analog image signal, and supplying the same to a data line selected by the vertical drive circuit. The first horizontal drive circuit includes a sampling latch circuit, a second latch circuit, a digital/analog conversion circuit, and a line selector for selecting the first and second digital image data in a time division manner in a predetermined period and outputting the same to the data line.Type: GrantFiled: December 8, 2005Date of Patent: June 14, 2011Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Masaki Murase, Yoshihiko Toyoshima, Kazuya Nomura, Masaaki Tonogai, Daisuke Ito
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Patent number: 7639034Abstract: The present invention relates to a flat display apparatus and a flat display apparatus testing method, and is, for example, applicable to a liquid crystal display apparatus where drive circuits are integrally formed on an insulating substrate. The present invention is capable of carrying out a reliable screening of defective pixels so as to effectively avoid deterioration in reliability even in cases where transistors with low withstand voltages are employed. A common line-side wiring pattern COM of wiring patterns LCC and COM of a capacitor of pixels is connected to a precharge circuit externally in an independent manner.Type: GrantFiled: June 28, 2004Date of Patent: December 29, 2009Assignee: Sony CorporationInventors: Masaki Murase, Yoshiharu Nakajima, Yoshitoshi Kida, Osamu Mitsui
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Publication number: 20090273593Abstract: A display device of a type capable of narrowing the pitch, realizing narrowing of the frame, and further lowering the power consumption and an electronic device using the device, wherein two horizontal drive circuits 13U and 13D employ an RGB selector scheme by storing three digital data in sampling and latch circuits, performing conversion processing to analog data three times by a common digital-to-analog conversion circuit during one horizontal period (H), selecting three analog data in the horizontal period in a time division manner, and outputting the same to data lines (signal lines).Type: ApplicationFiled: January 19, 2007Publication date: November 5, 2009Applicant: Sony CorporationInventors: Masaaki Tonogai, Yoshiharu Nakajima, Yoshitoshi Kida, Masaki Murase, Daisuke Ito