Patents by Inventor Masaki Murase

Masaki Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090213101
    Abstract: A display device able to amplify the same input as a power supply voltage of IC by using low temperature polysilicon having high threshold voltage and large variation and an electronic apparatus using the same, including MCK use level shifters 171-1 and 171-2 of a type where a reset operation is periodically necessary, a logic circuit 173 for using a level shift horizontal synchronization signal Hsync to input reset pulses for the MCK level shifters 171-1 and 171-2 having a period of N horizontal periods shifted in phase by M horizontal periods (note, M<N) to the level shifters 171-1 and 171-2 and outputting the resultant signals, and a function of selecting the circuit not performing the reset operation among outputs of the L number of level shifters 171-1 and 171-2 for each M horizontal periods and outputting a level shift master clock LSMCK as a last output signal.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 27, 2009
    Applicant: Sony Corporation
    Inventors: Masaki Murase, Daisuke Ito, Masaaki Tonogai, Yoshitoshi Kida, Yoshiharu Nakajima
  • Publication number: 20090058776
    Abstract: A display apparatus including: an effective pixel section having a plurality of pixel circuits arranged to form a matrix, each pixel circuit including a switching device through which pixel video data is written into the pixel circuit; a plurality of scan lines each provided for an individual one of rows of the pixel circuits arranged on the effective pixel section to control the conduction states of the switching devices; a plurality of capacitor lines each arranged for individual one of the rows connected to the pixel circuits; a plurality of signal lines each arranged for individual one of columns connected to the pixel circuits to propagate the pixel video data; a first driving circuit configured to selectively drive the scan lines and the capacitor lines; and a second driving circuit configured to drive the signal lines.
    Type: Application
    Filed: August 22, 2008
    Publication date: March 5, 2009
    Applicant: Sony Corporation
    Inventors: Kazuhisa Tomohiro, Masaki Murase, Takayuki Nakanishi, Naoyuki Itakura, Yoshitoshi Kida
  • Publication number: 20080122810
    Abstract: A flat display unit is applied to, for example, a liquid crystal display unit having a drive circuit integrally formed on an insulating substrate to sample tone data Dod, Dev in respective systems on corresponding horizontal drive circuits (23O, 23E) at a timing corresponding to sampling conducted when tone data (D11) is distributed to a plurality of systems.
    Type: Application
    Filed: June 23, 2004
    Publication date: May 29, 2008
    Applicant: Sony Corporation
    Inventors: Masaki Murase, Yoshiharu Nakajima, Yoshitoshi Kida
  • Patent number: 7372446
    Abstract: A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: May 13, 2008
    Assignee: Sony Corporation
    Inventors: Masaki Murase, Yoshiharu Nakajima
  • Publication number: 20060164364
    Abstract: The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D1) and forcedly switching the logical level of the input data (D1) at a predetermined timing during a quiescent period (T2) in which the input data is held at a constant logical level.
    Type: Application
    Filed: July 27, 2004
    Publication date: July 27, 2006
    Inventors: Masaki Murase, Yoshiharu Nakajima, Yoshitoshi Kida
  • Publication number: 20060139286
    Abstract: A display device and mobile terminal are provided.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 29, 2006
    Inventors: Yoshitoshi Kida, Yoshiharu Nakajima, Masaki Murase, Yoshihiko Toyoshima, Kazuya Nomura, Masaaki Tonogai, Daisuke Ito
  • Publication number: 20060017683
    Abstract: A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
    Type: Application
    Filed: August 19, 2005
    Publication date: January 26, 2006
    Inventors: Masaki Murase, Yoshiharu Nakajima
  • Patent number: 6958745
    Abstract: A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Sony Corporation
    Inventors: Masaki Murase, Yoshiharu Nakajima
  • Publication number: 20050024306
    Abstract: The present invention relates to a flat display apparatus and a flat display apparatus testing method, and is, for example, applicable to a liquid crystal display apparatus where drive circuits are integrally formed on an insulating substrate. The present invention is capable of carrying out a reliable screening of defective pixels so as to effectively avoid deterioration in reliability even in cases where transistors with low withstand voltages are employed. A common line-side wiring pattern COM of wiring patterns LCC and COM of a capacitor of pixels is connected to a precharge circuit externally in an independent manner.
    Type: Application
    Filed: June 28, 2004
    Publication date: February 3, 2005
    Applicant: SONY CORPORATION
    Inventors: Masaki Murase, Yoshiharu Nakajima, Yoshitoshi Kida, Osamu Mitsui
  • Publication number: 20040160404
    Abstract: Liquid crystal display devices suffer from low contrast at low temperature because the frequency characteristics of the liquid crystal dielectric constant are degraded.
    Type: Application
    Filed: December 23, 2003
    Publication date: August 19, 2004
    Inventors: Yoshiharu Nakajima, Masaki Murase
  • Publication number: 20040041771
    Abstract: A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
    Type: Application
    Filed: April 30, 2003
    Publication date: March 4, 2004
    Inventors: Masaki Murase, Yoshiharu Nakajima
  • Patent number: 6576689
    Abstract: A water based coating composition prepared by reacting an epoxy resin (A) having a bisphenol A skeletal structure and a carboxyl group-containing acrylic resin (B) in the presence of an amine compound to form an acrylic-modified epoxy resin (C), and neutralizing, and dispersing the acrylic-modified epoxy resin (C) into an aqueous medium, an amount of a quaternary ammonium salt in the acrylic-modified epoxy resin (C) being in the range of 3.0×10−4 mol or less per one gram of the resin.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: June 10, 2003
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Sumio Noda, Reijiro Nishida, Makoto Asakura, Masaki Murase
  • Publication number: 20020086923
    Abstract: A water based coating composition prepared by reacting an epoxy resin (A) having a bisphenol A skeletal structure and a carboxyl group-containing acrylic resin (B) in the presence of an amine compound to form an acrylic-modified epoxy resin (C), and neutralizing, and dispersing the acrylic-modified epoxy resin (C) into an aqueous medium, an amount of a quaternary ammonium salt in the acrylic-modified epoxy resin (C) being in the range of 3.0×10−4 mol or less per one gram of the resin.
    Type: Application
    Filed: October 17, 2001
    Publication date: July 4, 2002
    Inventors: Sumio Noda, Reijiro Nishida, Makoto Asakura, Masaki Murase
  • Patent number: 6155007
    Abstract: A spiral staircase includes a newel post and a plurality of steps which are mounted around the newel post. Each step has a surface tread. The tread is set up higher than the inner side. The slope of the tread at the outer side of the tread is sharper than at the inner side of the tread.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: December 5, 2000
    Inventor: Masaki Murase