Abstract: A circuit enabling device includes a processor configured to, when multiple predetermined setting values are written in a register in predetermined order, enable a module corresponding to the multiple predetermined setting values and the predetermined order, the multiple predetermined setting values being determined in advance for each of a multiple modules, the register being used to enable the multiple modules individually, the multiple modules being included in a user-specific circuit, the user-specific circuit including a general-purpose circuit and a user circuit, the user circuit including the multiple modules.

Abstract: A signal processing apparatus includes first and second processors that read and execute a program, and a memory. The first processor is configured to process plural color signals at one time and output the plural color signals in parallel. The memory is configured to temporarily store the plural color signals output from the first processor. The second processor is configured to sequentially read and process plural color signals processable at one time from the memory. The first and second processors are configured to process the plural color signals in units of bands including plural lines; after completion of processing of a first band, processing of a second band starts; and the first processor is configured to start processing the second band at a time point before completion of processing of the first band by the second processor, and at which color signals of the first band remain in the memory.

Abstract: An image processing apparatus includes a processing unit that shifts plural pieces of pixel data so as to suppress deviation in a sub-scanning direction at the time of image formation; a storage unit that stores the plural pieces of pixel data; and a converting unit that converts addresses of the plural pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of the shift process are stored in a cache memory used by the storage unit at once.

Abstract: A control apparatus of a light emitting diode includes a storage unit that stores table information indicating a combination of a magnitude and a cycle of luminance and the number of times of the combinations; and a control section that controls the light emitting diode in accordance with a control pattern in which the combination of the magnitude and the cycle of the luminance indicated in the table information is repeated up to the number of times of the combinations.

Abstract: An image processing apparatus includes a processor configured to process an image; a reading direct memory access controller (DMAC) configured to read data from the memory; a writing DMAC configured to write data to the memory, each DMAC configured to control direct memory access to a memory; an upper first-in first-out (FIFO) unit connected to the reading and writing DMACs and includes FIFOs of the number equal to the number of channels of each of the reading and writing DMACs and a lower FIFO unit connected between the upper FIFO unit and the processor and includes FIFOs that correspond to the FIFOs of the upper FIFO unit at a ratio of 1 upper FIFO unit to F lower FIFO units (F being an integer equal to 2 or larger).

Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

Abstract: An information processing device includes: a first processing unit that processes plural color signals at a time and outputs a processed plural color signals in parallel; a memory that temporarily stores the processed plural color signals outputted in parallel from the first processing unit; and a second processing unit that reads the processed plural color signals from the memory in order by a processable number at a time, the second processing unit being able to process a smaller number of color signals than the first processing unit at a time, wherein a reading speed from the memory is faster than a writing speed to the memory.

Abstract: An image processing apparatus includes a processor configured to process an image; a reading direct memory access controller (DMAC) configured to read data from the memory; a writing DMAC configured to write data to the memory, each DMAC configured to control direct memory access to a memory; an upper first-in first-out (FIFO) unit connected to the reading and writing DMACs and includes FIFOs of the number equal to the number of channels of each of the reading and writing DMACs and a lower FIFO unit connected between the upper FIFO unit and the processor and includes FIFOs that correspond to the FIFOs of the upper FIFO unit at a ratio of 1 upper FIFO unit to F lower FIFO units (F being an integer equal to 2 or larger).

Abstract: An image transmitting apparatus includes a transmitting unit and a controller. The transmitting unit transmits information according to a standard for video image communication. The controller exerts control in such a manner that still image information or information other than still image information is transmitted by using a bus for video image communication. The transmitting unit transmits the still image information or the information other than still image information in accordance with the control exerted by the controller.

Abstract: An image processing apparatus includes a trapping section that performs trapping on a received pixel, a digital filtering section that performs digital filtering on the pixel in parallel with the trapping using the trapping section, and a selection section that selects a result of the trapping using the trapping section and a result of the digital filtering using the digital filtering section.

Abstract: An image processing apparatus includes a processing unit that shifts plural pieces of pixel data so as to suppress deviation in a sub-scanning direction at the time of image formation; a storage unit that stores the plural pieces of pixel data; and a converting unit that converts addresses of the plural pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of the shift process are stored in a cache memory used by the storage unit at once.

Abstract: A control apparatus of a light emitting diode includes a storage unit that stores table information indicating a combination of a magnitude and a cycle of luminance and the number of times of the combinations; and a control section that controls the light emitting diode in accordance with a control pattern in which the combination of the magnitude and the cycle of the luminance indicated in the table information is repeated up to the number of times of the combinations.

Abstract: An electronic apparatus includes: an enlargement and reduction unit that enlarges or reduces an image input by direct memory access (DMA) transfer; and an image processing unit that, in a case where a size of an image after processing for enlargement or reduction by the enlargement and reduction unit is different from a size determined in advance as a size of an image after the processing, performs processing for adding pixels to the processed image or processing for deleting pixels of the processed image.

Abstract: An information processing device includes: a first processing unit that processes plural color signals at a time and outputs a processed plural color signals in parallel; a memory that temporarily stores the processed plural color signals outputted in parallel from the first processing unit; and a second processing unit that reads the processed plural color signals from the memory in order by a processable number at a time, the second processing unit being able to process a smaller number of color signals than the first processing unit at a time, wherein a reading speed from the memory is faster than a writing speed to the memory.

Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

Abstract: An electronic apparatus includes: an enlargement and reduction unit that enlarges or reduces an image input by direct memory access (DMA) transfer; and an image processing unit that, in a case where a size of an image after processing for enlargement or reduction by the enlargement and reduction unit is different from a size determined in advance as a size of an image after the processing, performs processing for adding pixels to the processed image or processing for deleting pixels of the processed image.

Abstract: A transfer control device includes: a write issuing unit that, after issuing to a transfer path a first write request for writing a last portion of data of a processing unit to a memory, issues a second write request for writing confirmation information to an area different from an area of the memory to which the data is written, the transfer path maintaining an order of write requests and an order of read requests and not maintaining an order between the write requests and the read requests; and a read issuing unit that issues to the transfer path a first read request for reading the confirmation information, after the second write request is issued, and issues to the transfer path a second read request for the data of the processing unit written to the memory, after reading the confirmation information in response to the first read request.

Abstract: An information processing device includes a memory access generating unit and an observation unit. The memory access generating unit generates pseudo memory access by using an arbitration unit in memory access. The observation unit observes a state of the pseudo memory access. The memory access generating unit changes a timing of occurrence of the pseudo memory access along a time axis.