Patents by Inventor Masaki Tamaru

Masaki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060276026
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 7, 2006
    Inventor: Masaki Tamaru
  • Publication number: 20060017087
    Abstract: A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor can be easily formed in the vicinity of the area where switching noise is generated, thereby effectively realizing the countermeasure for power source noise. In the process technique with advanced downsizing, a capacitor having large capacitance can be formed with a smaller area. In addition, the capacitor can be formed in the same process as the other device such as a transistor without adding any special step.
    Type: Application
    Filed: September 6, 2005
    Publication date: January 26, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Tamaru, Toshiyuki Moriwaki, Ryoichi Suzuki
  • Publication number: 20050194637
    Abstract: A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 8, 2005
    Inventor: Masaki Tamaru
  • Publication number: 20040075174
    Abstract: A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor can be easily formed in the vicinity of the area-where switching noise is generated, thereby effectively realizing the countermeasure for power source noise. In the process technique with advanced downsizing, a capacitor having large capacitance can be formed with a smaller area. In addition, the capacitor can be formed in the same process as the other device such as a transistor without adding any special step.
    Type: Application
    Filed: November 26, 2003
    Publication date: April 22, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Tamaru, Toshiyuki Moriwaki, Ryoichi Suzuki