Patents by Inventor Masaki Tsuji
Masaki Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12219766Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.Type: GrantFiled: August 9, 2023Date of Patent: February 4, 2025Assignee: Kioxia CorporationInventors: Masaki Tsuji, Yoshiaki Fukuzumi
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Publication number: 20250034293Abstract: The disclosure aims to provide a method for producing a refined polytetrafluoroethylene powder, in which a short-chain fluorine compound is reduced from low-molecular-weight polytetrafluoroethylene. Method for producing a refined polytetrafluoroethylene powder, including a step of reducing a short-chain fluorine compound from a low-molecular weight polytetrafluoroethylene powder obtained by radical polymerization. The step includes at least reducing a compound represented by following formula (1) to 179 ppb or less and a compound represented by following formula (2) to 6900 ppb or less. Formula (1): (H—(CF2)m—COO)pM1 (wherein m; M1; and p are as defined in the disclosure). Formula (2): (H—(CF2)n—SO3)qM2 (wherein n; M2; and q are as defined in the disclosure).Type: ApplicationFiled: October 11, 2024Publication date: January 30, 2025Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Chisato IGUCHI, Masaki KUBOCHI, Eiji MASUDA, Masayuki TSUJI, Jirou HIROMOTO
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Publication number: 20240397721Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: ApplicationFiled: August 7, 2024Publication date: November 28, 2024Applicant: Kioxia CorporationInventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
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Running pattern creation device and driving control method that uses running pattern creation device
Patent number: 12145642Abstract: A running pattern creation device includes: a coordinate system that is formed of a positional coordinate axis and a vehicle velocity axis; a stopping avoidance zone position holding unit 1 configured to hold positional information on a stopping avoidance zone of a vehicle 8; a vehicle condition holding unit 2 configured to hold at least information on respective accelerations at an acceleration time, a deceleration time and a coasting time with respect to specification of the vehicle 8; a braking pattern creation unit 3 configured to create a braking pattern that is a pattern for stopping the vehicle 8 at a position other than the stopping avoidance zone using the positional information and information on acceleration at the deceleration time; a coasting pattern creation unit 4 configured to create a coasting pattern that is a pattern for stopping the vehicle 8 at a position other than the stopping avoidance zone using the positional information and the information on acceleration at the coasting time; an obType: GrantFiled: August 31, 2020Date of Patent: November 19, 2024Assignee: Hitachi, Ltd.Inventors: Yuhi Tsutsumi, Keiji Maekawa, Atsushi Oda, Keiichi Katsuta, Masaki Tsuji -
Patent number: 12089410Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: GrantFiled: July 7, 2023Date of Patent: September 10, 2024Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
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Publication number: 20240251559Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Applicant: Kioxia CorporationInventors: Takashi ISHIDA, Yoshiaki FUKUZUMI, Takayuki OKADA, Masaki TSUJI
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Publication number: 20240155762Abstract: A flexible wiring board includes an insulating layer having a support surface extending in a first direction; a first sheet adhesive terminal positioned on the support surface; and a second sheet adhesive terminal positioned on the support surface. The shape of the first sheet adhesive terminal and the shape of the second sheet adhesive terminal are point-symmetric about a point on a straight fold line on which straight guide lines extending in the first direction lie.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: TOPPAN Inc.Inventor: Masaki TSUJI
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Patent number: 11980031Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
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Patent number: 11966126Abstract: A light control unit includes a wiring member including a mount section and an extending section, and a light control sheet that includes a light control layer formed between first and second transparent electrodes. The first transparent electrode has a first wiring region which is exposed from the light control layer, the second transparent electrode has a second wiring region which is exposed from the light control layer, the mount section is in the first wiring region and extends in a first direction along the edge portion of the first transparent electrode, the extending section extends from the mount section toward an outside of the first transparent electrode, the mount section has a first width along a first perpendicular direction perpendicular to the first direction, and the extending section has a second width greater than the first width of the mount section.Type: GrantFiled: November 14, 2022Date of Patent: April 23, 2024Assignee: TOPPAN Inc.Inventor: Masaki Tsuji
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Publication number: 20230389319Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Kioxia CorporationInventors: Masaki TSUJI, Yoshiaki FUKUZUMI
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Publication number: 20230363167Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: ApplicationFiled: July 7, 2023Publication date: November 9, 2023Applicant: Kioxia CorporationInventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
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Patent number: 11765904Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.Type: GrantFiled: September 12, 2022Date of Patent: September 19, 2023Assignee: Kioxia CorporationInventors: Masaki Tsuji, Yoshiaki Fukuzumi
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Publication number: 20230276629Abstract: A semiconductor device includes a body including conductive layers stacked and spaced from each other in a first direction and first and second areas along a second direction intersecting the first direction, an insulating portion extending along the directions in the areas and dividing the conductive layers in a third direction intersecting the directions, first columnar portions extending along the first direction in the first area and including a semiconductor layer, memory cells being formed at intersections between the conductive and semiconductor layers, second columnar portions extending along the first direction in the second area and including an insulator, third columnar portions extending along the first direction in the second area and including a semiconductor layer, and contacts extending along the first direction in the second area and connected to a conductive layer. The second portions are arranged along the insulating portion on both sides thereof in the third direction.Type: ApplicationFiled: September 1, 2022Publication date: August 31, 2023Inventors: Rikito KANAZAWA, Masaki TSUJI, Kojiro SHIMIZU
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Patent number: 11744075Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: GrantFiled: February 16, 2022Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
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Publication number: 20230079251Abstract: A light control unit includes a wiring member including a mount section and an extending section, and a light control sheet that includes a light control layer formed between first and second transparent electrodes. The first transparent electrode has a first wiring region which is exposed from the light control layer, the second transparent electrode has a second wiring region which is exposed from the light control layer, the mount section is in the first wiring region and extends in a first direction along the edge portion of the first transparent electrode, the extending section extends from the mount section toward an outside of the first transparent electrode, the mount section has a first width along a first perpendicular direction perpendicular to the first direction, and the extending section has a second width greater than the first width of the mount section.Type: ApplicationFiled: November 14, 2022Publication date: March 16, 2023Applicant: TOPPAN Inc.Inventor: Masaki TSUJI
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RUNNING PATTERN CREATION DEVICE AND DRIVING CONTROL METHOD THAT USES RUNNING PATTERN CREATION DEVICE
Publication number: 20230052777Abstract: A running pattern creation device includes: a coordinate system that is formed of a positional coordinate axis and a vehicle velocity axis; a stopping avoidance zone position holding unit 1 configured to hold positional information on a stopping avoidance zone of a vehicle 8; a vehicle condition holding unit 2 configured to hold at least information on respective accelerations at an acceleration time, a deceleration time and a coasting time with respect to specification of the vehicle 8; a braking pattern creation unit 3 configured to create a braking pattern that is a pattern for stopping the vehicle 8 at a position other than the stopping avoidance zone using the positional information and information on acceleration at the deceleration time; a coasting pattern creation unit 4 configured to create a coasting pattern that is a pattern for stopping the vehicle 8 at a position other than the stopping avoidance zone using the positional information and the information on acceleration at the coasting time; an obType: ApplicationFiled: August 31, 2020Publication date: February 16, 2023Applicant: HITACHI, LTD.Inventors: Yuhi TSUTSUMI, Keiji MAEKAWA, Atsushi ODA, Keiichi KATSUTA, Masaki TSUJI -
Publication number: 20230005958Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Applicant: Kioxia CorporationInventors: Masaki Tsuji, Yoshiaki Fukuzumi
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Patent number: 11528202Abstract: A packet flow monitoring device, a packet data extraction device, an extraction data aggregation device, and a program for efficiently and highly accurately monitoring a packet flow in a video or audio communication system constructed by an Ethernet (registered trademark) frame or IP packet network. This packet flow monitoring device includes: a packet data extraction device that replicates all passing packets that pass through one or a plurality of specific network switches on the network and extracts and aggregates some predetermined pieces of information in the replicated passing packets to form and output an extraction data report packet; and an extraction data aggregation device that receives the extraction data report packet, analyzes the extraction data report packet so as to aggregate the predetermined pieces of information in the replicated passing packets included in the extraction data report packet for each packet flow, and records the aggregated information as aggregation data.Type: GrantFiled: October 24, 2019Date of Patent: December 13, 2022Assignee: INTELLIGENT WAVE INCInventors: Tomofumi Koyama, Masahiro Kawaragi, Takuya Kurakake, Masaki Tsuji, Ryo Hasegawa, Keiichiro Katsuta, Naoya Suzuki
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Patent number: 11482537Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.Type: GrantFiled: July 28, 2020Date of Patent: October 25, 2022Assignee: Kioxia CorporationInventors: Masaki Tsuji, Yoshiaki Fukuzumi
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Publication number: 20220173124Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Applicant: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka