Patents by Inventor Masako Yoshida

Masako Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070148321
    Abstract: It is intended to provide a food or a drink with a favorable flavor which has an acidic nature, contains protein and minerals, and has been stabilized in dispersion without showing any protein aggregation or the like even in the absence of a stabilizer. It is also intended to provide such an acidic protein food or drink which shows no protein aggregation even in the case of using not only minerals hardly soluble in aqueous media but also highly soluble minerals. By using an acid-soluble soybean protein, it is possible to provide an acidic mineral-containing food or drink which has a high stability without resort to a stabilizer as an essential component. Owing to the acidic nature, moreover, a product having a refreshing flavor, which is never achieved by neutral foods or drinks, can be prepared.
    Type: Application
    Filed: March 8, 2005
    Publication date: June 28, 2007
    Inventors: Shigeru Ashida, Tsutomu Saito, Toshio Kiriyama, Masako Yoshida
  • Publication number: 20070049635
    Abstract: It is an object of the present invention to provide a diamine derivative, a process for producing the same, and a plant disease control agent containing the above-described compound as an active ingredient. According to the present invention, a diamine derivative represented by Formula (1), a process for producing the same, and a plant disease control agent containing the above-described compound as an active ingredient are provided.
    Type: Application
    Filed: October 20, 2004
    Publication date: March 1, 2007
    Inventors: Koichi Ebihara, Kunihiko Morizane, Naofumi Tomura, Ryutaro Ezaki, Masako Yoshida, Yuko Osada
  • Publication number: 20050238790
    Abstract: The present invention is intended to provide acidic gel foods containing soybean protein to diversify means of taking soybean protein in daily eating habits. Using the acid-soluble soybean protein as specified in the description, an aqueous solution or an alcohol-containing aqueous solution of the protein is adjusted to pH 3 to 4.5. Then an acid having 2 or more acid groups per molecule or its salt or a salt of another acid is added thereto and the mixture is heated to form a gel. Thus, acidic gel foods including a jelly-like food favorable as a food can be obtained.
    Type: Application
    Filed: August 28, 2003
    Publication date: October 27, 2005
    Inventors: Kyoko Ishimoto, Tsutomu Saito, Toshio Kiriyama, Eiji Iwaoka, Masako Yoshida
  • Patent number: 6677797
    Abstract: An integrated circuit has first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a high threshold value, while the second logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a low threshold value. An output switch circuit intervenes between the p-type FET and n-type FET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Masako Yoshida, Kazunori Ohuchi
  • Patent number: 6545323
    Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: April 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
  • Patent number: 6466054
    Abstract: A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Kazunori Ohuchi, Masako Yoshida
  • Patent number: 6455901
    Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: September 24, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Masako Yoshida
  • Publication number: 20020080663
    Abstract: An integrate circuit has a first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a high threshold value, while the second logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a low threshold value. An output switch circuit intervenes between the pMISFET and nMISFET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 27, 2002
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Masako Yoshida, Kazunori Ohuchi, Sachiko Ohuchi
  • Publication number: 20020056878
    Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
    Type: Application
    Filed: December 14, 2001
    Publication date: May 16, 2002
    Inventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
  • Patent number: 6349395
    Abstract: An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: February 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Ohuchi, Masako Yoshida, Yukihito Oowaki, Hiroshige Fujii, Masatoshi Sekine
  • Patent number: 6342408
    Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: January 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
  • Publication number: 20020010885
    Abstract: An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.
    Type: Application
    Filed: September 16, 1998
    Publication date: January 24, 2002
    Inventors: KAZUNORI OHUCHI, MASAKO YOSHIDA, YUKIHITO OOWAKI, HIROSHIGE FUJII, MASATOSHI SEKINE
  • Publication number: 20010052623
    Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.
    Type: Application
    Filed: March 13, 2001
    Publication date: December 20, 2001
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Masako Yoshida
  • Publication number: 20010024130
    Abstract: A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 27, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Kazunori Ohuchi, Masako Yoshida
  • Patent number: 6130461
    Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: October 10, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
  • Patent number: 5895956
    Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: April 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
  • Patent number: 5717625
    Abstract: In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: February 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hasegawa, Yukihito Oowaki, Shigeyoshi Watanabe, Ken-ichi Maeda, Mitsuo Saito, Masako Yoshida, Ryo Fukuda, Shinichiro Shiratake
  • Patent number: 5661678
    Abstract: A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Yoshida, Yukihito Oowaki, Takehiro Hasegawa, Kiyofumi Ochii, Masayuki Koizumi
  • Patent number: 4292353
    Abstract: A laminate having excellent flameproofing and low-smoke development is disclosed. The laminate comprises an urethane modified polyisocyanurate foam as a core material and an aluminum foil or sheet as a surface material piled on at least one surface of the foam through a self-adhesion of the foam and passes Grade 2 incombustibility according to Japanese Industrial Standard (JIS) A-1321 combustion test.
    Type: Grant
    Filed: November 13, 1978
    Date of Patent: September 29, 1981
    Assignee: Bridgestone Tire Co., Ltd.
    Inventors: Takashi Ohashi, Toru Okuyama, Akira Suzuki, Katsuhiko Arai, Minoru Kojima, Yoshiko Taniguchi, Masako Yoshida, Ryozo Sakata, Hideki Sugihara, Masashi Dobashi, Hirobumi Ohwada
  • Patent number: 4256846
    Abstract: A method of producing flameproof polyisocyanurate foams is disclosed. When the foam is produced by reacting an organic polyisocyanate with polyols as a modifying agent in the presence of an isocyanate trimerization catalyst, a blowing agent and other additives, a combination of particular low molecular weight diols with particular high molecular weight polyether polyols is used as the polyol in a special weight ratio and a special total amount per 100 parts by weight of the organic polyisocyanate in the presence of special combination of an alkali metal salt of a carboxylic acid and a tertiary amine compound as the catalyst.
    Type: Grant
    Filed: July 20, 1979
    Date of Patent: March 17, 1981
    Assignee: Bridgestone Tire Co., Ltd.
    Inventors: Takashi Ohashi, Toru Okuyama, Hiroshi Kaneda, Yoshiko Taniguchi, Masako Yoshida