Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: Disclosed is a nickel layer formed on a substrate by sputtering, in which nickel layer a percent ratio of an X-ray diffraction peak intensity of the (200) plane of the nickel layer to that of the (111) plane of the nickel layer is not less than 10%. This nickel layer has a reduced stress, and therefore, lessens a bending of a substrate. The nickel layer is formed by a process for sputtering nickel on a substrate, comprising supplying an argon gas into a vacuum chamber, adjusting a pressure of the argon gas in the vacuum chamber to a predetermined value, ionizing the argon gas, bombarding a target containing nickel with the ionized argon gas, to sputter nickel atoms, and depositing the sputtered nickel atoms onto the substrate, wherein the predetermined pressure of the argon gas is not lower than 12 mTorr.

Abstract: The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device includes a diode element for protecting a transistor against an overvoltage. A first region of p-type conductivity is formed on an upper surface of an n-type semiconductor substrate in which base and emitter regions of the transistor are formed. A second region of n.sup.+ -type conductivity whose impurity concentration is higher than that of the n-type semiconductor substrate is formed on its upper surface to be spaced apart from the first region. An insulating film is formed to cover the upper surface of the semiconductor substrate. Furthermore, a conductive film is formed to partially overlap the first and second regions through the insulating film. The first region serves as an anode, the second region serves as a cathode, and the conductive film serves as a gate electrode; thus an overvoltage protection diode is obtained.

Abstract: A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

Abstract: A method for forming electrodes with strong adhesion strength for a semiconductor device is provided. The adhesion strength between a Si substrate and a Ti film is made higher than the pulling stress of a Ni film. Before an electrode is formed using sputtering process, the natural oxide film grown on a semiconductor substrate is removed using an Ar reverse sputtering while the top surface of the silicon substrate is converted to an amorphous through a bombardment and introduction of Ar. While Ti is deposited, a Si-Ti amorphous layer is formed in the Si/Ti interface. In this case, the amount of Ar atoms is controlled less than 4.0.times.10.sup.14 atoms/cm.sup.2. The Ar amount also can be controlled by adjusting the conditions such as the output or cathodic voltage of Ar reverse sputtering and decreasing the absolute value of Ar in the amorphous Si layer. Also the Ar amount can be controlled by diffusing Ar atoms into the substrate at more than about 300.degree. C.

Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Abstract: A high withstanding voltage transistor is provided with a substrate with its main surface at least part of which is electrically insulated, and a plurality of MOS type field effect transistors of the same channel type that are formed on the insulated main surface of the substrate, the channel regions of the number of MOS type field effect transistors are electrically separated respectively, the gates of the plurality of MOS type field effect transistors are mutually connected electrically, between and among the plurality of MOS type field effect transistors, the source of one transistor is connected to the drain of another transistor, and connecting in series the plurality of MOS type field effect transistors, they are made into a single transistor, thereby dividing the voltage applied in between the drain and the source of this high withstanding voltage transistor with depletion layer of the respective transistors and in turn improving the withstanding voltage of the whole.