Abstract: An IC card 1 (portable card) having an integrated device. The IC card 1 includes a nonvolatile memory 12 and an encryption circuit 10. The nonvolatile memory 12 is accessed after the IC card 1 is placed in a radio wave zone to receive a power supply from a terminal apparatus through a radio wave. The encryption circuit 10 coordinates with a first terminal apparatus to perform a mutual authentication. The integrated device includes a nonvolatile memory 13 and an encryption circuit 11. The nonvolatile memory 13 is accessed after the IC card 1 is placed at a location close to an antenna in the first terminal apparatus and only after the IC card 1 receives a higher-level power supply from the antenna. The encryption circuit 11 coordinates with the terminal apparatus to perform a mutual authentication. Personal information that requires high security is stored in the nonvolatile memory 13 and the encryption circuit 11 performs a mutual authentication whenever the nonvolatile memory 13 is accessed.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: An IC card 1 having an integrated device includes a nonvolatile memory 12 and an encryption circuit 10. The nonvolatile memory 12 after the IC card 1 is placed in a radio wave zone to receive a power supply from a terminal apparatus through a radio wave. The encryption circuit 10 coordinates with a first terminal apparatus to perform a mutual authentication. The integrated device includes a nonvolatile memory 13 and an encryption circuit 11. The nonvolatile memory 13 is accessed after the IC card 1 is placed at a location close to an antenna in the first terminal apparatus and only after the IC card 1 receives a higher-level power supply from the antenna. The encryption circuit 11 coordinates with the terminal apparatus to perform a mutual authentication. Personal information that requires high security is stored in the nonvolatile memory 13 and the encryption circuit 11 performs a mutual authentication whenever the nonvolatile memory 13 is accessed.

Abstract: An IC card 1 (portable card) having an integrated device. The IC card 1 includes a nonvolatile memory 12 and an encryption circuit 10. The nonvolatile memory 12 is accessed after the IC card 1 is placed in a radio wave zone to receive a power supply from a terminal apparatus through a radio wave. The encryption circuit 10 coordinates with a first terminal apparatus to perform a mutual authentication. The integrated device includes a nonvolatile memory 13 and an encryption circuit 11. The nonvolatile memory 13 is accessed after the IC card 1 is placed at a location close to an antenna in the first terminal apparatus and only after the IC card 1 receives a higher-level power supply from the antenna. The encryption circuit 11 coordinates with the terminal apparatus to perform a mutual authentication. Personal information that requires high security is stored in the nonvolatile memory 13 and the encryption circuit 11 performs a mutual authentication whenever the nonvolatile memory 13 is accessed.

Abstract: An IC card 1 (portable card) having an integrated device. The IC card 1 includes a nonvolatile memory 12 and an encryption circuit 10. The nonvolatile memory 12 is accessed after the IC card 1 is placed in a radio wave zone to receive a power supply from a terminal apparatus through a radio wave. The encryption circuit 10 coordinates with a first terminal apparatus to perform a mutual authentication. The integrated device includes a nonvolatile memory 13 and an encryption circuit 11. The nonvolatile memory 13 is accessed after the IC card 1 is placed at a location close to an antenna in the first terminal apparatus and only after the IC card 1 receives a higher-level power supply from the antenna. The encryption circuit 11 coordinates with the terminal apparatus to perform a mutual authentication. Personal information that requires high security is stored in the nonvolatile memory 13 and the encryption circuit 11 performs a mutual authentication whenever the nonvolatile memory 13 is accessed.

Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0<y≦(4−x)×0.1 and 0.5<z<1.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: An IC card 1 (portable card) having an integrated device. The IC card 1 includes a nonvolatile memory 12 and an encryption circuit 10. The nonvolatile memory 12 is accessed after the IC card 1 is placed in a radio wave zone to receive a power supply from a terminal apparatus through a radio wave. The encryption circuit 10 coordinates with a first terminal apparatus to perform a mutual authentication. The integrated device includes a nonvolatile memory 13 and an encryption circuit 11. The nonvolatile memory 13 is accessed after the IC card 1 is placed at a location close to an antenna in the first terminal apparatus and only after the IC card 1 receives a higher-level power supply from the antenna. The encryption circuit 11 coordinates with the terminal apparatus to perform a mutual authentication. Personal information that requires high security is stored in the nonvolatile memory 13 and the encryption circuit 11 performs a mutual authentication whenever the nonvolatile memory 13 is accessed.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a taxis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0≦y≦(4−x)×0.1 and 0.5<z<1.

Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate

Abstract: A nondestructive read-out, nonvolatile ferroelectric field effect transistor (“FET”) memory in an integrated circuit, containing a thin film of polycrystalline crystallographically oriented ferroelectric material. Preferably, the material is polycrystalline c-axis oriented layered superlattice material. More preferably, it is c-axis oriented strontium bismuth tantalate or strontium bismuth tantalum niobate.

Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Abstract: An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 2000 Å. Typical gain sizes are 40 nanometers and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and an xylene exchange is preformed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 675° C. and 850° C.