Patents by Inventor Masamichi Ishihara
Masamichi Ishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11127657Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: January 21, 2020Date of Patent: September 21, 2021Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Patent number: 10748840Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.Type: GrantFiled: May 24, 2018Date of Patent: August 18, 2020Assignee: Invensas CorporationInventor: Masamichi Ishihara
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Publication number: 20200161223Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Inventor: Masamichi Ishihara
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Patent number: 10559521Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: December 19, 2018Date of Patent: February 11, 2020Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Publication number: 20190122961Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventor: Masamichi Ishihara
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Patent number: 10199310Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: December 22, 2017Date of Patent: February 5, 2019Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Publication number: 20180269141Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.Type: ApplicationFiled: May 24, 2018Publication date: September 20, 2018Inventor: Masamichi Ishihara
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Patent number: 9984961Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.Type: GrantFiled: October 14, 2013Date of Patent: May 29, 2018Assignee: Invensas CorporationInventor: Masamichi Ishihara
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Publication number: 20180122722Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: December 22, 2017Publication date: May 3, 2018Inventor: Masamichi Ishihara
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Patent number: 9887147Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: December 20, 2016Date of Patent: February 6, 2018Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Patent number: 9812621Abstract: A semiconductor device includes an electrical insulating layer with superior heat resistance, heat dissipation, and durability, and which is manufactured through a process with good cost performance and process performance. In a semiconductor device including a first substrate to which a semiconductor chip is mounted directly or indirectly, and a white insulating layer formed on a surface of the first substrate and functioning as a reflecting material, the semiconductor chip is an LED, at least the surface of the first substrate is made of a metal, and a stacked structure of the white insulating layer and a metal layer is formed by coating a liquid material, which contains SiO2 in the form of nanoparticles and a white inorganic pigment, over the surface of the first substrate and baking the coated liquid material.Type: GrantFiled: July 31, 2012Date of Patent: November 7, 2017Assignee: SHIKOKU INSTRUMENTATION CO., LTD.Inventors: Masamichi Ishihara, Kenshu Oyama, Shoji Murakami, Hitonobu Onosaka
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Patent number: 9698327Abstract: An LED illumination module in which LED bare chips are mounted on a mounting substrate at a high density, the module comprising many LED bare chips having the same specifications, the mounting substrate at least a surface of which is metal, and a reflection region in which the LED bare chips are sealed off with resin, wherein a surface of the reflection region of the mounting substrate is covered with an inorganic white insulating layer that functions as a reflection member, a unit LED chip group including a plurality of LED bare chips connected in series is disposed plural, the plural unit LED chip groups being connected in parallel, overall light flux is 10,000 lumens or more, and a mounting area density of the LED bare chips in the reflection region is 15 mm2/cm2 or more. An LED illumination apparatus including the LED illumination module is also provided.Type: GrantFiled: June 6, 2013Date of Patent: July 4, 2017Assignee: SHIKOKU INSTRUMENTATION CO., LTD.Inventors: Masamichi Ishihara, Kenshu Oyama, Shoji Murakami, Hitonobu Onosaka, Masato Shima
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Publication number: 20170162491Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.Type: ApplicationFiled: October 14, 2013Publication date: June 8, 2017Applicant: Invensas CorporationInventor: Masamichi Ishihara
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Publication number: 20170103938Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventor: Masamichi Ishihara
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Patent number: 9559041Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: June 18, 2015Date of Patent: January 31, 2017Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Patent number: 9252125Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.Type: GrantFiled: July 2, 2012Date of Patent: February 2, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
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Publication number: 20150287663Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventor: Masamichi Ishihara
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Patent number: 9093431Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.Type: GrantFiled: January 16, 2014Date of Patent: July 28, 2015Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masamichi Ishihara
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Publication number: 20150155459Abstract: An LED illumination module in which LED bare chips are mounted on a mounting substrate at a high density, the module comprising many LED bare chips having the same specifications, the mounting substrate at least a surface of which is metal, and a reflection region in which the LED bare chips are sealed off with resin, wherein a surface of the reflection region of the mounting substrate is covered with an inorganic white insulating layer that functions as a reflection member, a unit LED chip group including a plurality of LED bare chips connected in series is disposed plural, the plural unit LED chip groups being connected in parallel, overall light flux is 10,000 lumens or more, and a mounting area density of the LED bare chips in the reflection region is 15 mm2/cm2 or more. An LED illumination apparatus including the LED illumination module is also provided.Type: ApplicationFiled: June 6, 2013Publication date: June 4, 2015Applicant: SHIKOKU INSTRUMENTATION CO., LTD.Inventors: Masamichi Ishihara, Kenshu Oyama, Shoji Murakami, Hitonobu Onosaka, Masato Shima
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Patent number: 8988882Abstract: A circuit element is arranged on an organic substrate and connected to a wiring pattern arranged on the organic substrate. An internal connection electrode is formed on a conductive support body by electroforming so as to obtain a unitary block of the internal connection electrode and the support body. Each end of each of the internal connection electrodes connected into a unitary block by the support body is connected to the wiring pattern. After the circuit element is sealed by resin, the support body is peeled off, so as to obtain individual internal connection electrodes separately and the other end of each of the internal connection electrodes is used as an external connection electrode on the front surface while the external connection electrode on the rear surface is connected to the wiring pattern.Type: GrantFiled: March 24, 2010Date of Patent: March 24, 2015Assignees: Molex Japan Co., Ltd., Kagoshima UniversityInventors: Kenji Ohsawa, Rinkou Fukunaga, Katsuya Tsuruta, Kei Mizuta, Masamichi Ishihara