Patents by Inventor Masamichi Ishihara

Masamichi Ishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210095054
    Abstract: A method for producing a fluoropolymer, which includes polymerizing a fluoromonomer in an aqueous medium in the presence of a surfactant to provide a fluoropolymer, wherein the surfactant is a carboxylic acid type hydrocarbon-containing surfactant.
    Type: Application
    Filed: March 7, 2019
    Publication date: April 1, 2021
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Hirotoshi YOSHIDA, Taketo KATO, Kenji ICHIKAWA, Yohei FUJIMOTO, Yoshinori NANBA, Kengo ITO, Masahiro HIGASHI, Satoru YONEDA, Akiyoshi YAMAUCHI, Sumi ISHIHARA, Moe HOSOKAWA, Marina NAKANO, Yuuji TANAKA, Yosuke KISHIKAWA, Hirokazu AOYAMA, Masamichi SUKEGAWA, Taku YAMANAKA, Hiroyuki SATO
  • Publication number: 20210032381
    Abstract: A method for producing a fluoropolymer which includes polymerizing a fluoromonomer in an aqueous medium in the presence of a surfactant to provide a fluoropolymer, the surfactant being represented by the general formula (1): CR1R2R4—CR3R5—X-A, wherein R1 to R5 are each H or a monovalent substituent, with the proviso that at least one of R1 and R3 represents a group represented by the general formula: —Y—R6 and at least one of R2 and R5 represents a group represented by the general formula: —X-A or a group represented by the general formula: —Y—R6; and A is the same or different at each occurrence and is —COOM, —SO3M, or —OSO3M. Also disclosed is a surfactant for polymerization represented by the general formula (1), a method for producing a fluoropolymer using the surfactant and a composition including a fluoropolymer and the surfactant.
    Type: Application
    Filed: February 7, 2019
    Publication date: February 4, 2021
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Taketo KATO, Satoru YONEDA, Masahiro HIGASHI, Akiyoshi YAMAUCHI, Sumi ISHIHARA, Yosuke KISHIKAWA, Moe HOSOKAWA, Marina NAKANO, Hirotoshi YOSHIDA, Yoshinori NANBA, Kengo ITO, Chiaki OKUI, Kenji ICHIKAWA, Yohei FUJIMOTO, Hirokazu AOYAMA, Masamichi SUKEGAWA, Taku YAMANAKA, Hiroyuki SATO
  • Publication number: 20200392266
    Abstract: A method for producing a fluoropolymer, which includes polymerizing a fluoromonomer in an aqueous medium in the presence of a polymer (1), the polymer (1) including a polymerized unit derived from a monomer CX2?CY(—CZ2—O—Rf-A), wherein X is the same or different and is —H or —F; Y is —H, —F, an alkyl group, or a fluorine-containing alkyl group; Z is the same or different and is —H, —F, an alkyl group, or a fluoroalkyl group; Rf is a C1-C40 fluorine-containing alkylene group or a C—C100 fluorine-containing alkylene group and having an ether bond; and A is —COOM, —SO3M, or —OSO3M, wherein M is —H, a metal atom, —NR74, imidazolium optionally having a substituent, pyridinium optionally having a substituent, or phosphonium optionally having a substituent, wherein R7 is H or an organic group, providing that at least one of X, Y, and Z contains a fluorine atom.
    Type: Application
    Filed: March 1, 2019
    Publication date: December 17, 2020
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Yoshinori NANBA, Kenji ICHIKAWA, Yohei FUJIMOTO, Hirotoshi YOSHIDA, Hiroyuki SATO, Taketo KATO, Kengo ITO, Sumi ISHIHARA, Masahiro HIGASHI, Satoru YONEDA, Hirokazu AOYAMA, Masamichi SUKEGAWA, Yosuke KISHIKAWA, Takahiro TAIRA, Chiaki OKUI, Taku YAMANAKA
  • Patent number: 10748840
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventor: Masamichi Ishihara
  • Publication number: 20200161223
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventor: Masamichi Ishihara
  • Patent number: 10559521
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 11, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Publication number: 20190122961
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventor: Masamichi Ishihara
  • Patent number: 10199310
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 5, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Publication number: 20180269141
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 20, 2018
    Inventor: Masamichi Ishihara
  • Patent number: 9984961
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: May 29, 2018
    Assignee: Invensas Corporation
    Inventor: Masamichi Ishihara
  • Publication number: 20180122722
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventor: Masamichi Ishihara
  • Patent number: 9887147
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 6, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Patent number: 9812621
    Abstract: A semiconductor device includes an electrical insulating layer with superior heat resistance, heat dissipation, and durability, and which is manufactured through a process with good cost performance and process performance. In a semiconductor device including a first substrate to which a semiconductor chip is mounted directly or indirectly, and a white insulating layer formed on a surface of the first substrate and functioning as a reflecting material, the semiconductor chip is an LED, at least the surface of the first substrate is made of a metal, and a stacked structure of the white insulating layer and a metal layer is formed by coating a liquid material, which contains SiO2 in the form of nanoparticles and a white inorganic pigment, over the surface of the first substrate and baking the coated liquid material.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 7, 2017
    Assignee: SHIKOKU INSTRUMENTATION CO., LTD.
    Inventors: Masamichi Ishihara, Kenshu Oyama, Shoji Murakami, Hitonobu Onosaka
  • Patent number: 9698327
    Abstract: An LED illumination module in which LED bare chips are mounted on a mounting substrate at a high density, the module comprising many LED bare chips having the same specifications, the mounting substrate at least a surface of which is metal, and a reflection region in which the LED bare chips are sealed off with resin, wherein a surface of the reflection region of the mounting substrate is covered with an inorganic white insulating layer that functions as a reflection member, a unit LED chip group including a plurality of LED bare chips connected in series is disposed plural, the plural unit LED chip groups being connected in parallel, overall light flux is 10,000 lumens or more, and a mounting area density of the LED bare chips in the reflection region is 15 mm2/cm2 or more. An LED illumination apparatus including the LED illumination module is also provided.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 4, 2017
    Assignee: SHIKOKU INSTRUMENTATION CO., LTD.
    Inventors: Masamichi Ishihara, Kenshu Oyama, Shoji Murakami, Hitonobu Onosaka, Masato Shima
  • Publication number: 20170162491
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Application
    Filed: October 14, 2013
    Publication date: June 8, 2017
    Applicant: Invensas Corporation
    Inventor: Masamichi Ishihara
  • Publication number: 20170103938
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventor: Masamichi Ishihara
  • Patent number: 9559041
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 31, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Patent number: 9252125
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 2, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
  • Publication number: 20150287663
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Inventor: Masamichi Ishihara
  • Patent number: 9093431
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 28, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara