Patents by Inventor Masamichi Ishihara

Masamichi Ishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110062584
    Abstract: A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto.
    Type: Application
    Filed: May 7, 2009
    Publication date: March 17, 2011
    Inventor: Masamichi Ishihara
  • Publication number: 20110057325
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Application
    Filed: May 7, 2009
    Publication date: March 10, 2011
    Inventor: Masamichi Ishihara
  • Patent number: 7884466
    Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: February 8, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masamichi Ishihara, Fumihiko Ooka, Yoshihiko Ino
  • Publication number: 20110012269
    Abstract: A wiring electronic component of the present invention is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and in which the circuit element is connected to a wiring pattern on the back face and also connected, via vertical wiring, to external electrodes located on the front face opposite the wiring pattern. The wiring electronic component is composed of an electrically conductive support portion, which serves as an electroforming mother die, and a plurality of vertical wiring portions formed through electroforming such that they are integrally connected to the support portion.
    Type: Application
    Filed: March 27, 2009
    Publication date: January 20, 2011
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Masamichi Ishihara, Hirotaka Ueda
  • Publication number: 20110001235
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Application
    Filed: September 3, 2010
    Publication date: January 6, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka KAGAYA, Hidehiro TAKESHIMA, Masamichi ISHIHARA
  • Publication number: 20100295178
    Abstract: A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.
    Type: Application
    Filed: January 16, 2009
    Publication date: November 25, 2010
    Inventors: Masamichi Ishihara, Hirotaka Ueda
  • Patent number: 7838983
    Abstract: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: November 23, 2010
    Assignee: Kyushu Institute of Technology
    Inventor: Masamichi Ishihara
  • Patent number: 7825026
    Abstract: A gas inlet is disposed in a lower portion of a reaction chamber, a copper substrate is disposed in an upper portion thereof, and a tungsten catalytic body heated to 1600° C. is disposed midway between the two. Ammonia gas introduced from the gas inlet is decomposed by the tungsten catalytic body, a chemical species generated by the decomposition reacts with a surface of the copper substrate, and reduces and removes a contaminant on the copper surface, and a Cu3N thin film is formed on the copper substrate surface. This Cu3N film has the action of a film which prevents the oxidation of copper. This Cu3N film is thermally decomposed and removed when heated to temperatures of not less than 300° C., leaving a clean copper surface behind.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: November 2, 2010
    Assignee: Kyushu Institute of Technology
    Inventors: Akira Izumi, Masamichi Ishihara
  • Patent number: 7808093
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: October 5, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
  • Publication number: 20090224381
    Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
    Type: Application
    Filed: November 2, 2006
    Publication date: September 10, 2009
    Inventors: Masamichi Ishihara, Harufumi Kobayashi
  • Patent number: 7576413
    Abstract: The present invention provides a packaged stacked semiconductor device which includes bumps serving as external electrode terminals, the bumps being provided on both a front surface and a back surface of the device, and which is sacked on another semiconductor device, substrate, or board having electrode terminals so that the bumps are directly and electrically connected to the electrode terminals. The semiconductor device includes a semiconductor substrate having through-electrodes formed therein. The semiconductor device has, on the front surface side of the semiconductor substrate, a wiring layer connected to the through-electrodes, an insulating film formed on the wiring layer, additional wiring formed on the insulating film, post electrodes connected to the wiring, and external connection bumps connected to the post electrodes.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: August 18, 2009
    Assignee: Kyushu Institute of Technology
    Inventors: Masamichi Ishihara, Akira Izumi
  • Publication number: 20090140364
    Abstract: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen.
    Type: Application
    Filed: April 4, 2006
    Publication date: June 4, 2009
    Inventor: Masamichi Ishihara
  • Publication number: 20090072381
    Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
    Type: Application
    Filed: April 9, 2007
    Publication date: March 19, 2009
    Inventors: Masamichi Ishihara, Fumihiko Ooka, Yoshihiko Ino
  • Publication number: 20090050994
    Abstract: A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electrofomiing such that the internal connection electrodes are integrally connected to the support. First ends of the internal connection electrodes integrally connected by the support are connected to the wiring pattern. After the circuit element is resin-sealed, the support is removed so as to separate the internal connection electrodes from one another. Second ends of the internal connection electrodes are used as external connection electrodes on the front face, and external connection electrodes on the back face are connected to the wiring pattern.
    Type: Application
    Filed: October 28, 2008
    Publication date: February 26, 2009
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Masamichi ISHIHARA, Hirotaka UEDA
  • Publication number: 20080265430
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Application
    Filed: November 21, 2005
    Publication date: October 30, 2008
    Inventor: Masamichi Ishihara
  • Publication number: 20080223196
    Abstract: There is provided a semiconductor device having a music generation function for automatically generating music data from image data inputted without preparing music information in advance, and a mobile electronic device, a mobile telephone device, a spectacle instrument, and a spectacle instrument set using the same. The device includes a miniature camera 11 for continuously imaging an object and inputting image data for each frame; movement section identification means 21 for identifying the portion where an object has moved within each frame from the image data inputted by the miniature camera 11; music generation means 22 for generating music data corresponding to the position identified by the movement section identification means 21; and music output means 23 for outputting music data generated by the music generation means 22.
    Type: Application
    Filed: April 14, 2005
    Publication date: September 18, 2008
    Inventors: Shunsuke Nakamura, Masamichi Ishihara
  • Publication number: 20080061402
    Abstract: The present invention provides a packaged stacked semiconductor device which includes bumps serving as external electrode terminals, the bumps being provided on both a front surface and a back surface of the device, and which is sacked on another semiconductor device, substrate, or board having electrode terminals so that the bumps are directly and electrically connected to the electrode terminals. The semiconductor device includes a semiconductor substrate having through-electrodes formed therein. The semiconductor device has, on the front surface side of the semiconductor substrate, a wiring layer connected to the through-electrodes, an insulating film formed on the wiring layer, additional wiring formed on the insulating film, post electrodes connected to the wiring, and external connection bumps connected to the post electrodes.
    Type: Application
    Filed: November 29, 2005
    Publication date: March 13, 2008
    Inventors: Masamichi Ishihara, Akira Izumi
  • Publication number: 20070241437
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 18, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
  • Patent number: 6108264
    Abstract: An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
  • Patent number: RE37539
    Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Momose, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe