Patents by Inventor Masamichi Suzuki

Masamichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200246857
    Abstract: An object of the present invention is to extend a retention time of clutch oil and enable to efficiently cool clutch plates. A clutch hub (42) which is engaged with the clutch plates in an outer circumference is a press-molding article made from one steel sheet. In its inner circumferential surface, plural oil grooves (74-4) for cooling the clutch plates, which are extended to a shat direction and have a space in a circumferential direction. Each of dams (76) as a press-molding portion extending to radial inward is formed at an end portion of each of the oil groove (74-4). The press-molding of the dams (76) is performed by pressing a front surface side of the clutch hub (42) by punches (82) and disposing inner pressing tools (84) at a back surface side. The dams (76) comprise an upright front surface (76-1) and a back surface (76-2), which are a molding surface molded by using the molding tools.
    Type: Application
    Filed: August 10, 2018
    Publication date: August 6, 2020
    Applicant: UNIPRES CORPORATION
    Inventors: Daichi WATANABE, Masamichi MIWA, Ryosuke SUZUKI, Hideyuki NEZU
  • Publication number: 20200157768
    Abstract: A controller for a hydraulic excavator includes a first speed computation section that calculates a first speed of an arm cylinder from a value detected by an operation amount sensor; a second speed computation section that calculates a second speed from a value detected by a posture sensor and a third speed computation section calculates a third speed that is used as the speed of the arm cylinder in an actuator control section adapted to execute MC. The third speed computation section calculates the first speed as the third speed during the period between the detection of an input of operation for an arm by the operation amount sensor and predetermined time to, the third speed as a speed calculated from the first speed and the second speed during the period between t0 and time t1, and the second speed as the third speed at and after time t1.
    Type: Application
    Filed: September 13, 2017
    Publication date: May 21, 2020
    Inventors: Masamichi ITO, Hisami NAKANO, Yusuke SUZUKI, Akihiro NARAZAKI, Teruki IGARASHI
  • Patent number: 10601147
    Abstract: The present invention enables a core wire that contains a plurality of strands and a bonding object to be bonded more reliably using an ultrasonic bonding device that cantilever supports a pressing portion that performs ultrasonic bonding. A bonding object (for example, a terminal) is supported as on a stage, a core wire is overlaid on the bonding object, and the core wire and the bonding object are ultrasonically bonded in a state where the core wire is pressed toward the bonding object, using a pressing portion that is supported in cantilever fashion. During ultrasonic bonding, a pressing surface of the pressing portion is inclined in a pressing direction progressively toward a side where the pressing portion is cantilever supported, and also a bonding surface of the bonding object is inclined in the pressing direction progressively toward the side where the pressing portion is cantilever supported.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: March 24, 2020
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Tatsuo Tamagawa, Masamichi Yamagiwa, Takuya Suzuki, Daichi Miura
  • Publication number: 20200062362
    Abstract: A hybrid type vessel propulsion apparatus includes an engine, an electric motor, a propeller shaft that rotates together with a propeller, a first transmission path, a second transmission path, and a third transmission path. The first transmission path transmits power of the engine to the propeller shaft. The second transmission path transmits power of the electric motor to the propeller shaft without transmitting the power through the first transmission path. The third transmission path transmits a portion of the power of the engine, which has been transmitted from the first transmission path to the propeller shaft, to the electric motor in order for the electric motor to generate electricity.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 27, 2020
    Inventors: Daisuke NAKAMURA, Takayoshi SUZUKI, Masamichi FUJIWARA
  • Patent number: 10505108
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Jun Deguchi, Yoshifumi Nishi, Masamichi Suzuki, Fumihiko Tachibana, Makoto Morimoto, Yuichiro Mitani
  • Patent number: 10468237
    Abstract: An apparatus includes a row of substrate transfer devices 3 which can deliver a wafer W within a transfer chamber; and rows of process modules PM, arranged at right and left sides of the row of the substrate transfer devices along the row, configured to perform processes to the wafer W. The rows of the process modules PM are arranged such that each of the processes can be performed by at least two process modules PM. Thus, when a single process module PM cannot be used, the wafer W can be rapidly transferred to another process module PM which can perform the same process as performed in the corresponding process module. Therefore, even when the single process module PM cannot be used, the processes can be continued to the wafers W without stopping an operation of the apparatus, so that the number of wasted wafers W can be reduced.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 5, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Gomi, Tetsuya Miyashita, Shinji Furukawa, Koji Maeda, Masamichi Hara, Naoyuki Suzuki, Hiroshi Miki, Toshiharu Hirata
  • Publication number: 20190323721
    Abstract: A home appliance management system includes an outlet plug, a home appliance, and a control terminal. The outlet plug includes a position information storage which stores position information and a position information transmitting unit. The home appliance includes a position information receiving unit, a function providing unit, a type information storage, and a position and type information transmitting unit. The control terminal includes a position and type information receiving unit, a position and type information storage, an operating condition determining unit, and an operation controller.
    Type: Application
    Filed: November 28, 2017
    Publication date: October 24, 2019
    Inventors: Masamichi KACHI, Kazuki DOUMOTO, Tsuraki NAKAJIMA, Ayumi KONISHI, Masato SUZUKI
  • Patent number: 10446227
    Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kensuke Ota, Masamichi Suzuki, Reika Ichihara
  • Patent number: 10397139
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20190260141
    Abstract: The present invention enables a core wire that contains a plurality of strands and a bonding object to be bonded more reliably using an ultrasonic bonding device that cantilever supports a pressing portion that performs ultrasonic bonding. A bonding object (for example, a terminal) is supported as on a stage, a core wire is overlaid on the bonding object, and the core wire and the bonding object are ultrasonically bonded in a state where the core wire is pressed toward the bonding object, using a pressing portion that is supported in cantilever fashion. During ultrasonic bonding, a pressing surface of the pressing portion is inclined in a pressing direction progressively toward a side where the pressing portion is cantilever supported, and also a bonding surface of the bonding object is inclined in the pressing direction progressively toward the side where the pressing portion is cantilever supported.
    Type: Application
    Filed: October 12, 2017
    Publication date: August 22, 2019
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Tatsuo TAMAGAWA, Masamichi YAMAGIWA, Takuya SUZUKI, Daichi MIURA
  • Publication number: 20190088324
    Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kensuke OTA, Masamichi Suzuki, Reika Ichihara
  • Publication number: 20180324111
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 10044642
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20180090658
    Abstract: According to one embodiment, a thermoelectric conversion device includes a first stacked body comprising a plurality of first semiconductor layers of a first conductivity type, the first semiconductor layers spaced from each other in a first direction, a second stacked body comprising a plurality of second semiconductor layers of a second conductivity type, the second semiconductor layers spaced from each other in the first direction, and a first connection portion electrically connecting the first stacked body to the second stacked body, wherein the first stacked body has a plurality of first openings that extend inwardly of the first stacked body in the first direction, wherein a direction from the first stacked body to the second stacked body intersects the first direction, and wherein the second stacked body has a plurality of second openings extending inwardly of the second stacked body in the first direction.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 29, 2018
    Inventors: Yusuke KASAHARA, Miwa SATO, Yasuo AKATSUKA, Masamichi SUZUKI, Tomoaki INOKUCHI
  • Publication number: 20180082168
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 22, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao MARUKAME, Jun DEGUCHI, Yoshifumi NISHI, Masamichi SUZUKI, Fumihiko TACHIBANA, Makoto MORIMOTO, Yuichiro MITANI
  • Patent number: 9924117
    Abstract: According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Higashi, Takao Marukame, Masamichi Suzuki, Koichiro Zaitsu, Haiyang Peng, Hiroki Noguchi, Yuichiro Mitani
  • Patent number: 9584149
    Abstract: According to an embodiment, a comparator includes a first transistor, a second transistor, an output stage, and a node group. The first transistor is configured to operate when a first voltage applied thereto exceeds a first threshold value, and is disposed in an input stage. The second transistor is configured to operate when a second voltage applied thereto exceeds a second threshold value and is disposed in the input stage. The output stage is configured to perform voltage switching and output according to the change in the magnitude relationship between the first voltage and the second voltage. The node group is configured to, during a non-operational state in which the first voltage and the second voltage are not compared, vary at least either the first threshold value or the second threshold value.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Yuuichiro Mitani
  • Patent number: 9530855
    Abstract: This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Yusuke Higashi, Riichiro Takaishi, Mitsuhiro Tomita, Kiwamu Sakuma, Yuichiro Mitani
  • Publication number: 20160294406
    Abstract: According to an embodiment, a comparator includes a first transistor, a second transistor, an output stage, and a node group. The first transistor is configured to operate when a first voltage applied thereto exceeds a first threshold value, and is disposed in an input stage. The second transistor is configured to operate when a second voltage applied thereto exceeds a second threshold value and is disposed in the input stage. The output stage is configured to perform voltage switching and output according to change in magnitude relationship between the first voltage and the second voltage. The node group is configured to, during a non-operational state in which the first voltage and the second voltage are not compared, vary at least either the first threshold value or the second threshold value.
    Type: Application
    Filed: June 7, 2016
    Publication date: October 6, 2016
    Inventors: Masamichi SUZUKI, Yuuichiro MITANI
  • Publication number: 20160149834
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: December 18, 2015
    Publication date: May 26, 2016
    Inventors: Kosuke TATSUMURA, Atsuhiro KINOSHITA, Hirotaka NISHINO, Masamichi SUZUKI, Yoshifumi NISHI, Takao MARUKAME, Takahiro KURITA