Patents by Inventor Masamichi Suzuki

Masamichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160088243
    Abstract: According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 24, 2016
    Inventors: Yusuke HIGASHI, Takao Marukame, Masamichi Suzuki, Koichiro Zaitsu, Haiyang Peng, Hiroki Noguchi, Yuichiro Mitani
  • Publication number: 20160079434
    Abstract: This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.
    Type: Application
    Filed: July 7, 2015
    Publication date: March 17, 2016
    Inventors: Masamichi SUZUKI, Yusuke HIGASHI, Riichiro TAKAISHI, Mitsuhiro TOMITA, Kiwamu SAKUMA, Yuichiro MITANI
  • Patent number: 9246709
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 9083423
    Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Hirotaka Nishino, Kazuya Matsuzawa, Izumi Hirano, Takao Marukame, Yusuke Higashi, Takahiro Kurita, Yuki Sasaki, Yuichiro Mitani
  • Patent number: 8849219
    Abstract: In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n?1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Deguchi, Shouhei Kousai, Yousuke Hagiwara, Masamichi Suzuki, Atsuhiro Kinoshita, Takao Marukame
  • Patent number: 8809970
    Abstract: A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate and being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Suzuki, Tatsuo Shimizu, Atsuhiro Kinoshita
  • Publication number: 20140227989
    Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.
    Type: Application
    Filed: December 17, 2013
    Publication date: August 14, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masamichi SUZUKI, Hirotaka NISHINO, Kazuya Matsuzawa, Izumi HIRANO, Takao MARUKAME, Yusuke HIGASHI, Takahiro KURITA, Yuki SASAKI, Yuichiro MITANI
  • Patent number: 8681034
    Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito
  • Patent number: 8681033
    Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito
  • Publication number: 20140055189
    Abstract: According to an embodiment, a mixer circuit includes first transistors each having a charge storage layer, a second transistor, a group of first nodes, and an output node. The first transistors as a pair receive a differential signal having a first frequency. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which those signals are mixed, to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency.
    Type: Application
    Filed: July 1, 2013
    Publication date: February 27, 2014
    Inventors: Masamichi SUZUKI, Atsuhiro Kinoshita, Takao Marukame, Shouhei Kousai, Jun Deguchi
  • Publication number: 20130252559
    Abstract: In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n?1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun DEGUCHI, Shouhei Kousai, Yousuke Hagiwara, Masamichi Suzuki, Atsuhiro Kinoshita, Takao Marukame
  • Patent number: 8450208
    Abstract: In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki
  • Publication number: 20130076551
    Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.
    Type: Application
    Filed: June 27, 2012
    Publication date: March 28, 2013
    Inventors: Takao MARUKAME, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito
  • Publication number: 20130076550
    Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.
    Type: Application
    Filed: June 28, 2012
    Publication date: March 28, 2013
    Inventors: Takao MARUKAME, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito
  • Publication number: 20130069440
    Abstract: According to one embodiment, an incoming circuit using a magnetic resonant coupling includes an incoming coil which receives magnetic field energy transmitted from an outgoing coil under conditions of energy power transmission by the magnetic resonant coupling, and an incoming circuit which comprises a variable capacitor and a rectifier circuit and which outputs, as a direct-current voltage, the magnetic field energy received by the incoming coil. A capacitance of the variable capacitor is automatically controlled to change in an analog form along with the change of the direct-current voltage and to keep the transmission efficiency of the magnetic field energy at a fixed value by directly feeding back the direct-current voltage to the variable capacitor.
    Type: Application
    Filed: June 29, 2012
    Publication date: March 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Hirotaka NISHINO, Masamichi SUZUKI, Atsuhiro KINOSHITA
  • Publication number: 20120326244
    Abstract: A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate with being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.
    Type: Application
    Filed: July 20, 2012
    Publication date: December 27, 2012
    Inventors: Masamichi SUZUKI, Tatsuo Shimizu, Atsuhiro Kinoshita
  • Patent number: 8338901
    Abstract: Certain embodiments provide a solid-state imaging device including: a photoelectric converting unit that includes a semiconductor layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type, converts incident light entering a first surface of the semiconductor substrate into signal charges, and stores the signal charges; a readout circuit that reads the signal charges stored by the photoelectric converting unit; an antireflection structure that is provided on the first surface of the semiconductor substrate to cover the semiconductor layer of the photoelectric converting unit, includes a fixed charge film that retains fixed charges being non-signal charges, and prevents reflection of the incident light; and a hole storage region that is provided between the photoelectric converting unit and the antireflection structure, and stores holes being non-signal charges.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Risako Ueno, Kazuhiro Suzuki, Hideyuki Funaki, Yoshinori Iida, Tatsuo Shimizu, Masamichi Suzuki
  • Publication number: 20120117354
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 10, 2012
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20120077341
    Abstract: In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
    Type: Application
    Filed: April 7, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki
  • Publication number: 20110175187
    Abstract: Certain embodiments provide a solid-state imaging device including: a photoelectric converting unit that includes a semiconductor layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type, converts incident light entering a first surface of the semiconductor substrate into signal charges, and stores the signal charges; a readout circuit that reads the signal charges stored by the photoelectric converting unit; an antireflection structure that is provided on the first surface of the semiconductor substrate to cover the semiconductor layer of the photoelectric converting unit, includes a fixed charge film that retains fixed charges being non-signal charges, and prevents reflection of the incident light; and a hole storage region that is provided between the photoelectric converting unit and the antireflection structure, and stores holes being non-signal charges.
    Type: Application
    Filed: September 3, 2010
    Publication date: July 21, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Risako Ueno, Kazuhiro Suzuki, Hideyuki Funaki, Yoshinori Iida, Tatsuo Shimizu, Masamichi Suzuki