Patents by Inventor Masana Harada
Masana Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7253031Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: November 2, 2004Date of Patent: August 7, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6979874Abstract: A plurality of p anode regions are formed at one surface of an n? substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n? substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.Type: GrantFiled: October 30, 2002Date of Patent: December 27, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masana Harada
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Patent number: 6897493Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: June 10, 2003Date of Patent: May 24, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20050062073Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: November 2, 2004Publication date: March 24, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6867437Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: August 20, 2002Date of Patent: March 15, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6693310Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: February 17, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20030201455Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: June 10, 2003Publication date: October 30, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20030057482Abstract: A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n− substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.Type: ApplicationFiled: October 30, 2002Publication date: March 27, 2003Inventor: Masana Harada
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Publication number: 20030006456Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: August 20, 2002Publication date: January 9, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6501146Abstract: A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n− substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.Type: GrantFiled: December 10, 1997Date of Patent: December 31, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masana Harada
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Patent number: 6445012Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: September 3, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6331466Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.Type: GrantFiled: May 2, 2000Date of Patent: December 18, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Takahashi, Hidenori Nishihara, Masana Harada, Tadaharu Minato
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Publication number: 20010045566Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: May 23, 2001Publication date: November 29, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6323508Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (7), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.Type: GrantFiled: May 30, 2000Date of Patent: November 27, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Takahashi, Hidenori Nishihara, Masana Harada, Tadaharu Minato
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Patent number: 6265735Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: December 30, 1998Date of Patent: July 24, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6177713Abstract: An anode electrode metal layer composed of aluminum is formed in a region on the inner side than an anode layer formed on a main surface of a semiconductor substrate. Thus, an impurity diffusion region from the innermost circumferential surface of said surface of field limiting innermost circumferential layer to the outermost circumferential surface of the anode electrode metal layer may be used as an electrical resistance. As a result, the hole density distributed from the bottom side of the field limiting innermost circumferential layer to a cathode layer when forward bias is applied may be reduced. As a result, when a reverse bias is applied, locally great recovery current passed from a cathode layer to the bottom of field limiting innermost circumferential layer may be restrained. Therefore, a diode capable of preventing destruction of a field limiting innermost circumferential layer when a reverse bias is applied may be provided.Type: GrantFiled: February 1, 1999Date of Patent: January 23, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinji Aono, Masana Harada
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Patent number: 6107650Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N.sup.+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N.sup.+ emitter layer (206). Furthermore, the ladder-like N.sup.+ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.Type: GrantFiled: February 14, 1995Date of Patent: August 22, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Takahashi, Hidenori Nishihara, Masana Harada, Tadaharu Minato
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Patent number: 5977570Abstract: A pin diode is formed by a p.sup.+ collector region, an n type buffer region, an n.sup.- region and an n.sup.+ cathode region. A trench is formed from the surface of n.sup.+ cathode region through n.sup.+ cathode region to reach n.sup.- region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n.sup.+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n.sup.+ cathode region. An anode electrode is formed to be electrically connected to p.sup.+ collector region. The n.sup.+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: July 18, 1996Date of Patent: November 2, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 5559348Abstract: A semiconductor device which allows an ON-state voltage to be lower than that of a conventional device and a method of manufacturing such a device. In this semiconductor device, a gate electrode is formed to have a planar area of its region covering a first base layer larger than that of its region covering a second base layer, thereby increasing a cathode short-circuit ratio of a cathode-shorted diode equivalent to this semiconductor device. As a result, a lower voltage than conventional ON-state can be obtained.Type: GrantFiled: June 5, 1995Date of Patent: September 24, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kiyoto Watabe, Ikunori Takata, Masana Harada
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Patent number: 5547886Abstract: In an SOI substrate including a single-crystal Si substrate (1b), an oxide film (20) and a single-crystal Si substrate (1a), there is formed an stepped wall surface (8) by selective removal of the single-crystal Si substrate (1a) to provide a thick oxide film (5) on the stepped wall surface (8). When a VDMOS (100) is formed in an active region of the single-crystal Si substrate (1b) above which the single-crystal Si substrate (1a) is absent and an MOS (101) having a thin oxide film (22) is formed in the single-crystal Si substrate (1a), the oxide film (5) is not damaged because it is thick. The thickness of the single-crystal Si substrate (1a) enables to be designed in accordance with the required thickness of the MOS (101).Type: GrantFiled: December 6, 1994Date of Patent: August 20, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masana Harada