Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.

Abstract: A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.

Abstract: A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure.

Abstract: A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.

Abstract: In a set of hybrid vehicles including first and second hybrid vehicles connected in series, each of the hybrid vehicles having an electric storage device, a controller for the first hybrid vehicle comprises a monitoring unit configured to detect an amount of electric charge stored in the electric storage device of the first hybrid vehicle, a communication unit configured to carryout communication with a communication unit of at least the second hybrid vehicle to acquire an amount of electric charge stored in the electric storage device of the second hybrid vehicle, and a control unit configured to determine load shares of the first and second hybrid vehicles during operation of the first and second hybrid vehicles, on the basis of the amount of electric charge stored in the electric storage devices thereof.

Abstract: In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

Abstract: In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

Abstract: A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

Abstract: A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

Abstract: Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit.

Abstract: To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage.

Abstract: A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder.