Patents by Inventor Masanobu Shirakawa
Masanobu Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11367489Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.Type: GrantFiled: December 18, 2020Date of Patent: June 21, 2022Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
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Patent number: 11361820Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: GrantFiled: January 7, 2021Date of Patent: June 14, 2022Assignee: KIOXIA CORPORATIONInventors: Tomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
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Patent number: 11347584Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.Type: GrantFiled: March 3, 2020Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Hideki Yamada, Marie Takada, Ryo Yamaki, Osamu Torii, Naomi Takeda
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Patent number: 11334432Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: GrantFiled: November 6, 2020Date of Patent: May 17, 2022Assignee: KIOXIA CORPORATIONInventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
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Publication number: 20220148657Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 11322210Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.Type: GrantFiled: August 27, 2020Date of Patent: May 3, 2022Assignee: KIOXIA CORPORATIONInventors: Marie Takada, Masanobu Shirakawa
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Publication number: 20220130458Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA
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Publication number: 20220130468Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
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Patent number: 11315420Abstract: A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers are each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. The server generates list information including the target information from the first and second monitoring devices, and transmits the list information to the first and second monitoring devices. The first controller further generates a map according to the list information received from the server, and displays the map on the first display.Type: GrantFiled: April 2, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Marie Takada, Masanobu Shirakawa
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Patent number: 11315643Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.Type: GrantFiled: June 4, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa
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Publication number: 20220115070Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
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Publication number: 20220108754Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.Type: ApplicationFiled: December 17, 2021Publication date: April 7, 2022Applicant: Toshiba Memory CorporationInventor: Masanobu SHIRAKAWA
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Publication number: 20220101901Abstract: According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.Type: ApplicationFiled: December 14, 2021Publication date: March 31, 2022Applicant: Kioxia CorporationInventors: Naomi TAKEDA, Masanobu SHIRAKAWA
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Publication number: 20220101924Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: Toshiba Memory CorporationInventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
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Patent number: 11289167Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.Type: GrantFiled: November 25, 2020Date of Patent: March 29, 2022Assignee: KIOXIA CORPORATIONInventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
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Publication number: 20220093199Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Publication number: 20220093198Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.Type: ApplicationFiled: January 26, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Naomi TAKEDA, Ryo YAMAKI, Masanobu SHIRAKAWA
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Publication number: 20220075521Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Inventors: Masanobu SHIRAKAWA, Tokumasa HARA
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Publication number: 20220075562Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.Type: ApplicationFiled: March 3, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Yasuhiko KUROSAWA, Naomi TAKEDA, Masanobu SHIRAKAWA, Yasuyuki USHIJIMA, Shinichi KANNO
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Publication number: 20220077175Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Takuya FUTATSUYAMA