Patents by Inventor Masanobu Shirakawa

Masanobu Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 11024386
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama
  • Patent number: 11017863
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 11004523
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Coiporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Publication number: 20210134360
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 6, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tomonori TAKAHASHI, Masanobu SHIRAKAWA, Osamu TORII, Marie TAKADA
  • Publication number: 20210110875
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
  • Publication number: 20210110874
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Masanobu SHIRAKAWA, Tsukasa TOKUTOMI, Marie TAKADA
  • Patent number: 10978165
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes a memory cell and a controller having a memory storing a write parameter used in a write operation to the memory cell. The controller instructs the non-volatile semiconductor memory to perform the write operation to the memory cell using the write parameter, receives, from the non-volatile semiconductor memory, a result of checking of the write parameter which is obtained in the write operation and updates the write parameter stored in the memory on the basis of the result of checking of the write parameter.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Masanobu Shirakawa
  • Patent number: 10978157
    Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
  • Publication number: 20210104282
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA
  • Publication number: 20210096949
    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.
    Type: Application
    Filed: November 6, 2020
    Publication date: April 1, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Kengo KUROSE, Masanobu SHIRAKAWA, Marie TAKADA
  • Publication number: 20210089233
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.
    Type: Application
    Filed: March 12, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Yoshihiro UEDA, Naomi TAKEDA, Masanobu SHIRAKAWA, Marie TAKADA
  • Publication number: 20210090643
    Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA
  • Publication number: 20210089392
    Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA, Ryo YAMAKI, Osamu TORII, Naomi TAKEDA
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10957405
    Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideki Yamada, Masanobu Shirakawa
  • Publication number: 20210082483
    Abstract: According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.
    Type: Application
    Filed: March 5, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Naomi TAKEDA, Masanobu SHIRAKAWA
  • Publication number: 20210082510
    Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 18, 2021
    Inventors: Hideki YAMADA, Marie TAKADA, Masanobu SHIRAKAWA
  • Publication number: 20210082519
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Publication number: 20210082524
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki AKAMINE, Masanobu SHIRAKAWA, Tokumasa HARA