Patents by Inventor Masanobu Zenke

Masanobu Zenke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6593233
    Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: July 15, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Kazuki Miyazaki, Kazunobu Shigehara, Masanobu Zenke
  • Patent number: 6258690
    Abstract: In a method of manufacturing a semiconductor device having a capacitor portion consisting of a lower electrode, a dielectric film, and an upper electrode on a semiconductor substrate, a silicon film is formed on a surface of the lower electrode and a surface of an insulating film adjacent to the lower electrode. Annealing is preformed in an atmosphere containing nitrogen or ammonia to nitride the silicon film. A silicon nitride film is formed by LP-CVD.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: July 10, 2001
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 6204076
    Abstract: A fin type storage node electrode projects from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge, and testing elements for evaluating properties of the layers of the storage node electrode are concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: March 20, 2001
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 6146966
    Abstract: In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the "crystal nucleation" process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: November 14, 2000
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Hirohito Watanabe, Fumiki Aiso, Shuji Fujiwara, Masanobu Zenke
  • Patent number: 6020248
    Abstract: A stacked storage capacitor of a dynamic random access memory cell has an accumulating electrode increased in surface area by growing hemispherical silicon grains on an amorphous silicon strip, and a barrier layer of titanium nitride is previously formed between a source region of an associated field effect transistor and the amorphous silicon strip so that phosphorus is hardly diffused from the amorphous silicon strip into the source region.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: February 1, 2000
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5969381
    Abstract: Testing elements are disposed to prevent breakage by locating them such that their entire lower surface is formed directly on an insulating layer of a semiconductor device. These testing elements may be used with a fin type storage node electrode projecting from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge. These testing elements may be used for evaluating properties of the layers of the storage node electrode and be concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5959326
    Abstract: In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: September 28, 1999
    Assignee: NEC Corporation
    Inventors: Fumiki Aiso, Hirohito Watanabe, Toshiyuki Hirota, Masanobu Zenke, Shuji Fujiwara
  • Patent number: 5956595
    Abstract: In order to fabricate a semiconductor device having a stacked capacitor cell, a silicon substrate is first prepared. A lower capacitor electrode having a porous surface is then formed on the silicon substrate. Following this, the lower capacitor electrode is selectively covered with a titanium nitride film. Further, a dielectric film of a material, exhibiting high permittivity or feroelectricity, is deposited on said titanium nitride film, and an upper capacitor electrode is deposited on the dielectric film.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: September 21, 1999
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5897983
    Abstract: In a method for forming an annular-shaped and vertically extending bottom electrode of a memory cell capacitor, a conductive film is formed on an inter-layer insulator. A photo-resist material is applied on the conductive film to form a photo-resist film thereon. The photo-resist film is patterned by a photo-lithography using a mask which includes a transparent plate-like body and a phase shifting film selectively provided on a predetermined region of the transparent plate-like body to form an annular-shaped and vertically extending photo-resist pattern over the conductive film. The conductive film is subjected to an anisotropic etching, in which the annular-shaped and vertically extending photo-resist pattern is used as a mask, to form an annular-shaped and vertically extending bottom electrode under the annular-shaped and vertically extending photo-resist pattern. The annular-shaped and vertically extending photo-resist pattern is removed.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: April 27, 1999
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Tomomi Kurokawa, Masanobu Zenke, Kazuki Yokota
  • Patent number: 5851581
    Abstract: A contact is formed in an insulating film covering on a silicon substrate and thereafter an amorphous silicon film is deposited thereon at 400.degree. to 500.degree. C. by using disilane. A tungsten film is then formed and etched back to form a tungsten plug through etch-back.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: December 22, 1998
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5843840
    Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventors: Kazuki Miyazaki, Kazunobu Shigehara, Masanobu Zenke
  • Patent number: 5811333
    Abstract: On a semiconductor substrate (1), a polysilicon layer (3) of a random crystal structure is formed. The polysilicon layer (3) is treated by an etchant to provide a roughened surface (3a) of the polysilicon layer (3). The roughened surface (3a) is formed along grains of a random crystal structure and extends over all of top and side surfaces of the polysilicon layer (3). Thus, the polysilicon layer (3) serves as a lower electrode (4) having an increased surface area. A capacitor insulator layer (5) is deposited on the lower electrode (4). An upper electrode (6) is deposited on the capacitor insulator layer (5).
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: September 22, 1998
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5798569
    Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventors: Kazuki Miyazaki, Kazunobu Shigehara, Masanobu Zenke
  • Patent number: 5700710
    Abstract: Crystal grains of a lower polysilicon layer is grown through an annealing or an ion-implantation before separation of the lower polysilicon layer into doped silicon pieces, an upper polysilicon layer with small crystal grains is deposited over the doped silicon pieces so as to wave at long intervals, and the upper polysilicon layer is roughened so as to wave at short intervals, thereby increasing the surface area of an accumulating electrode of a capacitor.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: December 23, 1997
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5700738
    Abstract: In a method and an apparatus for producing a semiconductor device, means is provided for adding an oxidizing gas to an inactive gas to be fed to the sides of a wafer. Before a metal film is formed on the front of the wafer, the oxidizing gas oxidizes silicon exposed on the sides and rear of the wafer and unprotected from a raw material gas, thereby forming a silicon oxide film. Hence, even when the metal film is formed on the front of the wafer via an adhesion layer, it is scarcely formed on the sides and rear of the wafer and turns out a minimum of particles. This prevents the metal film from easily coming off without resorting to a great amount of inactive gas.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: December 23, 1997
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5691229
    Abstract: A cylindrical storage node electrode increases the surface area and, accordingly, the capacitance of a storage capacitor of a dynamic random access memory cell, and a silicon nitride layer is used as an etching stopper which is removed before completion of the storage capacitor so that hydrogen surely cures crystal defects during a hydrogen treatment carried out after patterning metal wirings.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: November 25, 1997
    Assignee: NEC Corporation
    Inventors: Kenji Okamura, Masanobu Zenke
  • Patent number: 5525540
    Abstract: In a method for manufacturing a silicon layer, a silicon layer is grown simultaneously with doping impurities into the silicon layer. Then, an impurity diffusion preventing layer is grown by interrupting this silicon layer growing step at least one time.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: June 11, 1996
    Assignee: NEC Corporation
    Inventors: Masanobu Zenke, Fumiki Aisou
  • Patent number: 5521126
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a wiring layer on the surface of a semiconductor substrate, depositing a silicone film on the whole surface of the semiconductor substrate including the wiring layer by a CVD method and exposing the silicone film to oxidative plasma with enhanced frequencies including components of 1 MHz or less to change to a silicon oxide film, the depositing step and exposing step being alternately repeated in the same apparatus till the silicon oxide film having any desired thickness is obtained. The resulting silicon oxide film has the smooth surface and the high density.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: May 28, 1996
    Assignee: NEC Corporation
    Inventors: Kenji Okamura, Masanobu Zenke, Yasuhide Den
  • Patent number: 5441594
    Abstract: A contact hole reaching a diffusion layer 2 provided on the surface of a silicon substrate 1 is formed by etching an insulating film 3. At this time, a surface layer 2a formed on the surface of the diffusion layer 2 is removed within a film forming unit by utilizing chlorine trifluoride gas. Next, a polycrystalline silicon film 4 is formed within tile same film forming equipment. Thus, the surface of an electrically conductive layer (including a semiconductor layer) covered with the insulating film is selectively exposed by the etching process and, prior to the formation of the film (including oxidized layer), connected to the exposed surface of the electrically conductive layer, the surface layer formed on the surface of the electrically conductive layer, which includes a naturally oxidized film, damage, contaminated substances or the like, can be completely removed.
    Type: Grant
    Filed: February 24, 1993
    Date of Patent: August 15, 1995
    Assignee: NEC Corporation
    Inventor: Masanobu Zenke
  • Patent number: 5372962
    Abstract: A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Ichirou Honma, Hirohito Watanabe, Masanobu Zenke