Patents by Inventor Masanori Fujibayashi

Masanori Fujibayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE
    Publication number: 20100180095
    Abstract: The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer.
    Type: Application
    Filed: November 28, 2006
    Publication date: July 15, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masanori Fujibayashi, Nobuo Higaki, Kazushi Kurata, Tomoko Matsui
  • Semiconductor circuit for arithmetic processing and arithmetic processing method
    Patent number: 7296048
    Abstract: There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: November 13, 2007
    Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, I & F, Inc.
    Inventors: Tadahiro Ohmi, Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi, Koji Kotani, Tadashi Shibata, Takahisa Nitta
  • Semiconductor circuit for arithmetic processing and arithmetic processing method
    Publication number: 20050080835
    Abstract: There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
    Type: Application
    Filed: August 15, 2003
    Publication date: April 14, 2005
    Inventors: Tadahiro Ohmi, Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi, Koji Kotani, Tadashi Shibata, Takahisa Nitta
  • Semiconductor circuit for arithmetic operation and method of arithmetic operation
    Patent number: 6728745
    Abstract: There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: April 27, 2004
    Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, I & F, Inc.
    Inventors: Tadahiro Ohmi, Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi, Koji Kotani, Tadashi Shibata, Takahisa Nitta