Abstract: A power semiconductor apparatus is provided with power controlling semiconductor modules connected in parallel to each other. Each power controlling semiconductor module controls driving of a power semiconductor device. The power semiconductor apparatus includes a transmission circuit and a reception circuit provided in one and another power controlling semiconductor modules, respectively. The transmission circuit transmits a predetermined communication signal to another power controlling semiconductor module based on a predetermined activation signal generated by one power controlling semiconductor module. The reception circuit receives the transmitted communication signal, and controls driving control operation of another power controlling semiconductor module based on the received communication signal.

Abstract: A power semiconductor apparatus is provided with power controlling semiconductor modules connected in parallel to each other. Each power controlling semiconductor module controls driving of a power semiconductor device. The power semiconductor apparatus includes a transmission circuit and a reception circuit provided in one and another power controlling semiconductor modules, respectively. The transmission circuit transmits a predetermined communication signal to another power controlling semiconductor module based on a predetermined activation signal generated by one power controlling semiconductor module. The reception circuit receives the transmitted communication signal, and controls driving control operation of another power controlling semiconductor module based on the received communication signal.

Abstract: A controller for controlling a power device in response to an input signal includes a first signal generator for generating a first signal in response to the input signal; a level shifter for changing an output level of the first signal to a value which is a function of a first main power supply potential in order to produce a second signal; and a first control signal generator for generating the control signal for a first semiconductor device in response to the second signal. The level shifter includes at least one level shifting semiconductor element wherein the semiconductor element is controlled by the first signal and the at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of the first and a value of a second main power supply potential.

Abstract: A semiconductor device comprising at least one power device, at least one control element for controlling the power device(s), a plurality of first terminals connected to the power device(s), a plurality of second terminals connected to the control element(s), a support member having a heat sink disposed on a lower surface of the support member and the power device(s), control element(s), and first and second terminals arranged on the upper surface of the support member, and a package including the support member for sealing the devices and one end of the terminals such that first and second terminals protrude from different sides of the package. The arrangement allows a reduced size three-phase motor drive controller, a reduction in noise interference to the control element, and reduction in terminal pitch size.

Abstract: A controller for power devices which is not required to individually insulate high and low potential portions and to include an insulated power supply is disclosed. An external controller (6) is connected to a second internal control circuit (4) which is in turn connected to a level shift circuit (5) and a gate electrode of a transistor (Q2). Power supply voltage (V1) is applied to the second internal control circuit (4) for operation thereof. The level shift circuit (5) is connected to a first internal control circuit (3) which is in turn connected to a gate electrode of a transistor (Q1) and a charge pump circuit (7). Control of a first semiconductor circuit is made through the level shift means in response to an input signal generated on the basis of a second main power supply potential, thereby achieving increased responsiveness of the power devices to a control signal and improved integration.

Abstract: A controller for power devices which is not required to individually insulate high and low potential portions and to include an insulated power supply is disclosed. An external controller (6) is connected to a second internal control circuit (4) which is in turn connected to a level shift circuit (5) and a gate electrode of a transistor (Q2). Power supply voltage (V1) is applied to the second internal control circuit (4) for operation thereof. The level shift circuit (5) is connected to a first internal control circuit (3) which is in turn connected to a gate electrode of a transistor (Q1) and a charge pump circuit (7). Control of a first semiconductor circuit is made through the level shift means in response to an input signal generated on the basis of a second main power supply potential, thereby achieving increased responsiveness of the power devices to a control signal and improved integration.

Abstract: A capacitor (C) and a Zener diode (ZD2) are connected in parallel to a high-voltage side drive circuit (2). when a Zener voltage (VZD2) is set 5V, a voltage which is charged up in the capacitor (C) is determined by the Zener voltage (VZD2). Hence, it is only necessarv to set a voltage (VCC) in a loxv-voltage d.c. power source (4) at a value which is higher than (VZD2+VD+VCE), where VD is a forward-direction voltage to a diode (Di) and VCE is an ON-voltage to a low-voltage side switching device (Q1). Since a variation in a charging voltage which is supplied to a high-voltage side drive circuit is suppressed, it is possible to drive a switching device with 5V.

Abstract: The drain electrodes of HNMOS transistors (2) and (3) are connected to the first ends of resistors (4) and (5), and to the inputs of inverter circuits (6) and (7) respectively. The outputs of the inverter circuits (6) and (7) are connected to the inputs of a protection circuit (27). The outputs of the protection circuit (27) are connected to the set and reset inputs of a flip-flop circuit (10A). The protection circuit (27) serves to prevent the malfunction of the flip-flop circuit (10A) from occurring and is formed by a logic gate. Having this configuration high potential side power device driving circuit is provided wherein the pulse widths of signals input to the gate electrodes of transistors for level shift can be set optionally, the lag time of the signal is not caused by a passage through a filter circuit, and the malfunction of a flip-flop circuit can be prevented from occurring due to a dv/dt current without lowering the response performance of a power device.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: In a control circuit for controlling a power transistor included in a power device, the transistor is turned-off when a drop of a control voltage level or overcurrent in the power transistor is detected. Signals for discriminating the overcurrent from the voltage drop are generated and individually outputted from the control circuit, whereby the reason why the transistors were turned-off can be monitored. After a predetermined time period has passed from the overcurrent had been detected, the transistor is automatically turned-on to recover the operation of the transistor. A capacitor for supplying the control power voltage is re-charged during the time period. It is not necessary to carefully determine the on/off timings of the input signal for waiting the recovery of the control power voltage.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: A TSD (8) is provided in the vicinity of an IGBT (1), and reference voltages (VR1 to VR5) are provided to the negative inputs of comparators (51 to 55) as a function of a temperature detection signal (S8). A sense terminal (3) of the IGBT is connected to the positive inputs of the comparators (51 to 55) in common. An output signal (S51) of the comparator (51) and output signals (S72 to S75) of signal judging circuits (72 to 75) having received the output signals (S52 to S55) are applied to the input of an NOR gate (6) for on/off control of the IGBT. The signal judging circuits (72 to 75) normally output an L-level judgment signal (S7) and output an H-level judgment signal (S7) when the input signal is at the H level for periods of time that are not shorter than allowable durations (.DELTA.t2 to .DELTA.t5 ), respectively. This provides an overcurrent protective device for a power device which performs overcurrent protective operation adapted for a practical safe operating area of the power device.

Abstract: Free wheeling diodes are protected against an overcurrent. When counter electromotive forces E.sub.VU and E.sub.WU established in a tri-phase motor cause regenerative currents I.sub.V1 and I.sub.W1 to flow to transistors Q4 and Q6, and to a protection diode D2, it is decided that the protection diode D2 is in overcurrent state. In response to the decision, the transistors Q4 and Q6 are turned off, which allows that regenerative currents I.sub.V2 and I.sub.W2 flow in protection diodes D3 and D5 because of the counter electromotive forces E.sub.VU and E.sub.WU. The energies of the regenerative currents I.sub.V2 and I.sub.W2 are regenerated at a capacitor C. Thus, since a regenerative current which once passed by only one protection diode is divided into two current flows into two protection diodes, the overcurrent state is terminated.

Abstract: In an overcurrent protection circuit of a power device, an analog switch (4) connects a negative input of a comparator (3) to a reference voltage VREF1 or another reference voltage VREF2 depending on a control signal (S5) from a timer (5). A positive input of the comparator (3) receives voltage drop value (VS). The timer (5) is triggered by a leading edge of an input signal (IN) to output the control signal (S5) to the analog switch (4). The control signal (S5) directs the analog switch (4) to connect the reference voltage VREF2 to the negative input of the comparator (3) only during a transient state estimated period (T) and to connect the reference voltage VREF1 to the negative input of the comparator (3) out of the transient state estimated period (T).

Abstract: A first insulating layer (32), a first shield pattern (iii) and a second insulating layer (112) are layered on an aluminum substrate (31) in that order. A first and a second power switching element (1, 2), which are in totem pole like connection, are provided On the second insulating layer (112). Also provided on the second insulating layer (112) are a first and a second control circuit (13, 14), through a second and a third shield pattern (101, 104) as well as a third and a fourth insulating layer (105, 106). The first shield pattern (111) is kept at a certain reference potential, because .+-.he first shield pattern (11) connected to a power source terminal N. The second and the third shield pattern (101, 104) are kept at potentials corresponding to the potentials of the output terminals of the first and the second power switching element (1, 2), respectively.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: Upper and lower arm monitoring circuits (13U, 13L) monitor on/off states of upper and lower arm switching devices (2U, 2L). The on/off command signal generating part (7) generates command signals for directing on/off of the switching devices (2U, 2L). Upper and lower arm decision circuits (12U, 12L) alternatively drive the upper and lower arm switching devices (2U, 2L) under predetermined conditions on the basis of monitoring signals from the monitoring circuit (13U, 13L) and the command signals. Thus, a dead time is necessarily automatically provided between the turning-off of one of the switching devices (2U, 2L) and the turning-on of the other of the switching devices (2U, 2L), without setting an upper and lower arm dead time for the command signals.

Abstract: On an insulating layer (32) formed on a metal substrate (31), cascode-connected power switching elements (1-6) are provided and shield patterns (101-104) are formed. Control circuits (13-18) for the switching elements (1-6) are formed on insulating layers (105, 106) formed on the shield patterns (101-104) which are fixed to potentials responsive to potentials of output electrodes of the corresponding switching elements (1-6). The control circuits (13-18) and the corresponding shield patterns (101-104) are in capacity coupling. Thus, noise arises in the control circuits (13-18) with respect to the metal substrate (31) when noise is applied to current paths of the switching elements (1-6) with respect to the metal substrate (31). As a result, viewing from the output electrodes of the switching elements (1-6), the control circuits (13-18) have noise equivalent to nothing.