Patents by Inventor Masanori Furuta

Masanori Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220255730
    Abstract: According to one embodiment, a secure computing method includes setting a coefficient selected from a ring of integers Q based on first data X, generating n pieces of first fragment data from the first data X based on the coefficient, causing a learning model held in the computing device to learn the first fragment data, generating n pieces of second fragment data from second data Z based on the coefficient, performing, by each of the n computing devices, inference based on the second fragment data using the learning model, and obtaining decoded data dec by decoding k pieces of inference result data. The coefficient is set to make each of the n pieces of first fragment data less than a maximum value of the ring of integers Q.
    Type: Application
    Filed: September 8, 2021
    Publication date: August 11, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mari MATSUMOTO, Masanori FURUTA
  • Publication number: 20220179688
    Abstract: According to an embodiment, an information processing device is configured to assign a first computing device one or more first tasks of processing respective one or more first partial data of a plurality of partial data included in an n-dimensional target data, n being an integer greater than or equal to 2, the target data being to be processed using a neural network, the one or more first partial data including first data and second data adjacent to the first data in a direction of m-dimension, m being an integer satisfying 1?m?n; and instruct the first computing device to execute a second task included in the one or more first tasks, according to an execution status of second partial data of the plurality of partial data included in the target data, the second partial data being executed by the second computing device.
    Type: Application
    Filed: August 27, 2021
    Publication date: June 9, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota TAMURA, Mizuki ONO, Masanori FURUTA
  • Publication number: 20220004815
    Abstract: A learning system according to an embodiment includes a model generation device and n calculation devices. The model generation device includes a splitting unit, a secret sharing unit, and a share transmission unit. The splitting unit splits m×n pieces of training data into n groups each including m training data pieces, the n groups corresponding to the respective n calculation devices on one-to-one basis. The secret sharing unit generates m distribution training data pieces for each of the n groups by distributing using a secret sharing scheme and generates distribution training data for each of the m training data pieces in an i-th group among the n groups, using an i-th element Pi among n elements P1, P2, . . . , Pi, . . . , Pn, by distributing using the secret sharing scheme. The share transmission unit transmits corresponding m distribution training data pieces to each of the n calculation devices.
    Type: Application
    Filed: February 19, 2021
    Publication date: January 6, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mari MATSUMOTO, Masanori FURUTA
  • Publication number: 20210097438
    Abstract: According to one embodiment, an anomaly detection device includes predicted value calculation unit, an anomaly degree calculation unit, a second predicted value calculation unit, a determination value calculation unit, and an anomaly determination unit. The first predicted value calculation unit calculates a first model predicted value from a correlation model obtained by first machine learning, the anomaly degree calculation unit calculates an anomaly degree, the second predicted value calculation unit calculates a second model predicted value from a time series model obtained by second machine learning, the determination value calculation unit calculates a divergence degree, and the anomaly determination unit determines whether an anomaly occurs or not.
    Type: Application
    Filed: September 8, 2020
    Publication date: April 1, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mari MATSUMOTO, Masanori FURUTA
  • Patent number: 10320372
    Abstract: An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation operation while the pulse of the pulse signal is output and holds an oscillation operation state at a point of time where the output of the pulse is stopped.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 11, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Yoshioka, Akihide Sai, Kohei Onizuka, Masanori Furuta
  • Patent number: 10281592
    Abstract: According to an embodiment, a radiation measuring apparatus includes a detector, comparators, a threshold controller, counters, and a generator. The detector includes plural detecting elements each configured to convert energy of incident radiation into a first electrical signal. The comparators correspond to the respective detecting elements, each comparator being configured to output a second electrical signal when a level of the corresponding first electrical signal is not less than a threshold. The threshold controller is configured to supply a first value as the threshold to the respective comparators at a first time, and supply a second value as the threshold to the respective comparators at a second time. The counters correspond to the respective comparators, each counter being configured to count the corresponding second electrical signal. The generator is configured to generate a pulse height frequency distribution of the radiation by using counts of the counters.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 7, 2019
    Assignee: Canon Medical Systems Corporation
    Inventors: Go Kawata, Shunsuke Kimura, Hideyuki Funaki, Masanori Furuta, Tetsuro Itakura
  • Patent number: 10218364
    Abstract: A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 26, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihide Sai, Masanori Furuta, Tetsuro Itakura, Satoshi Kondo, Hidenori Okuni, Tuan Thanh Ta
  • Patent number: 10177796
    Abstract: A receiver has a receiving unit to receive a radio signal, a signal detector to detect a reception signal in each of a plurality of set periods shifted in time to be overlapped in a partial period, and a demodulating unit to perform demodulation processing based on the reception signal. The signal detector has a smoothing unit to smooth the output signal of the receiving unit in each of the plurality of set periods, a comparing unit to output a signal obtained by comparing a level of the smoothed signal, with a threshold value, and an initializing unit to initialize the signal smoothed by the smoothing processing unit, every time the comparing unit compares the smoothed signal with the threshold value, and the demodulating unit performs the demodulation processing based on the smoothed signal determined to be the threshold value or more by the comparing unit.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya Matsuno, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
  • Patent number: 10171067
    Abstract: A waveform shaping filter according to an embodiment includes at least one filter stage and a control circuit. The filter stage includes a differentiation signal generation circuit, a proportional signal generation circuit, and an adder circuit. The differentiation signal generation circuit generates a differentiation signal obtained by amplifying a differentiation component of an input signal. The proportional signal generation circuit generates a proportional signal obtained by amplifying the input signal. The adder circuit outputs an output signal obtained by adding the proportional signal and the differentiation signal. The control circuit compares the output signal and a first detection level, detects at least one of an overshoot and an undershoot of the output signal, and controls a time constant of the filter stage, based on a detection result.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Hideyuki Funaki, Go Kawata, Hirokatsu Shirahama
  • Publication number: 20180343004
    Abstract: An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation operation while the pulse of the pulse signal is output and holds an oscillation operation state at a point of time where the output of the pulse is stopped.
    Type: Application
    Filed: March 7, 2018
    Publication date: November 29, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Yoshioka, Akihide Sai, Kohei Onizuka, Masanori Furuta
  • Patent number: 10128881
    Abstract: A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Kondo, Akihide Sai, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
  • Publication number: 20180278407
    Abstract: A wireless communication apparatus has a transmitter, a signal processor, and ADPLL circuitry. The transmitter to modulate transmission data using a local oscillation signal to generate a wireless signal to be transmitted from an antenna. The signal processor to generate the transmission data and to supply the generated transmission data to the transmitter. The ADPLL (All Digital Phase-Locked Loop) circuitry to generate the local oscillation signal by ADPLL processing and to supply digital information correlated with an input sensing signal to the signal processor.
    Type: Application
    Filed: September 18, 2017
    Publication date: September 27, 2018
    Inventors: Akihide SAI, Hidenori OKUNI, Masanori FURUTA, Satoshi KONDO
  • Publication number: 20180269885
    Abstract: An oscillator has an oscillator, an integer phase detector, a random number generator, an edge selector, a fractional phase detector, an offset correction arithmetic unit, and a phase error generator. The oscillator generates an oscillation signal having an oscillation frequency in accordance with a phase error signal. The integer phase detector detects an integer phase of the oscillation signal. The random number generator generates a random number. The edge selector outputs a phase difference signal indicating a phase difference between a phase of a reference signal and a phase of the oscillation signal, or indicating a phase difference acquired by offsetting the phase difference. The fractional phase detector detects a fractional phase of the oscillation signal based on the phase difference signal. The offset correction arithmetic unit computes an offset correction value in accordance with the random number. The phase error generator generates the phase error signal.
    Type: Application
    Filed: September 15, 2017
    Publication date: September 20, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi KONDO, Akihide Sai, Masanori Furuta
  • Patent number: 10041830
    Abstract: A radiation detection apparatus according to an embodiment includes a radiation detector that detects radiation; a first measurer that measures energy of the radiation from the radiation detected by the radiation detector; and a second measurer that measures the number of times that the radiation detector detects the radiation.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 7, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Go Kawata, Hideyuki Funaki, Masanori Furuta, Hirokatsu Shirahama, Tetsuro Itakura
  • Patent number: 10014895
    Abstract: A receiver has an oscillator to output an oscillation signal, a receiver to perform reception processing of a reception signal, a phase frequency detector to output a first signal in response to a phase and a frequency of the oscillation signal so as to generate a second signal indicating a reference phase, a differentiator to generate a third signal being a difference between the first signal and the second signal, an oscillator controller to generate a fourth signal for controlling a phase and a frequency of the oscillator, a phase initializer to output an initialization signal for synchronizing a phase of the second signal with a phase of the first signal, a trigger signal generator to output a trigger signal indicating timing with which the phase initializer outputs the initialization signal, and a power supply controller to control whether to supply a power supply voltage.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 3, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Kondo, Akihide Sai, Masanori Furuta
  • Patent number: 9973202
    Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 15, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Yoshioka, Masanori Furuta, Hiroshi Kubota
  • Patent number: 9954702
    Abstract: A radio communication device has a local oscillator to generate a local signal, a first mixer to mix a binary continuous phase frequency shift keying signal and the local signal so as to generate a baseband signal, a first filter to remove an unnecessary frequency component included in the baseband signal, a delay device to delay an output signal of the first filter by one symbol, and a wave detector to demodulate the continuous phase frequency shift keying signal, wherein a modulation index m of the continuous phase frequency shift keying signal is a value expressed by m=n+k where 0<n<1 is satisfied and k is an integer of 0 or more, and a frequency of the local signal is a frequency shifted by a frequency corresponding to 0 or 1 of the continuous phase frequency shift keying signal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hidenori Okuni, Akihide Sai, Masanori Furuta
  • Patent number: 9952334
    Abstract: A pulse detection circuit according to an embodiment includes a conversion circuit, a delay circuit, first and second comparators, a latch, and a generation circuit. The conversion circuit converts an input signal into a thermometer code signal. The delay circuit outputs a delay signal being the thermometer code signal delayed by a predetermined delay time. The first comparator (The second comparator) compares the thermometer code signal with the delay signal and outputs an increase signal (a decrease signal) indicating whether the input signal is larger (smaller) than the input signal before the delay time. Based on the increase signal and the decrease signal, the latch outputs an increase-decrease signal indicating whether the input signal is increasing or decreasing. Based on the thermometer code signal and the increase-decrease signal, the generation circuit generates a pulse detection signal and a pileup detection signal.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokatsu Shirahama, Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki
  • Patent number: 9945962
    Abstract: According to an embodiment, a signal processor includes an integrator, a differentiator, a zero cross detector, a pile-up detector, an event interval detector, a counter, and a creator. The integrator is configured to calculate charge of current from a photoelectric converter for an incident radiation. The differentiator is configured to calculate a differential value of the current. The zero cross detector is configured to detect a zero cross of the differential value. The pile-up detector is configured to detect pile-up of the current based on the zero cross. The event interval detector is configured to detect, based on the zero cross and pile-up, an event interval of the radiation entering. The counter is configured to count, based on the charge and pile-up, the respective numbers of events according to the charge and the event interval. The creator is configured to create histograms for the numbers of events.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: April 17, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Funaki, Shunsuke Kimura, Go Kawata, Tetsuro Itakura, Masanori Furuta
  • Publication number: 20180083647
    Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 22, 2018
    Inventors: Kentaro YOSHIOKA, Masanori FURUTA, Hiroshi KUBOTA