Patents by Inventor Masanori Furuta
Masanori Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160380758Abstract: A wireless communication apparatus has an analog control loop circuitry to generate an analog control signal which adjusts a phase of a voltage-controlled oscillation signal, an integrator to integrate the analog control signal, a phase adjuster to adjust a phase of the voltage-controlled oscillation signal, a digital control loop circuitry, in a first mode, to match a frequency of the voltage-controlled oscillation signal to a frequency of the received signal based on an output signal of the phase adjuster, and in a second mode, to generate a digital control signal which is opposite in phase to the analog control signal and has a frequency, a voltage-controlled oscillator to generate the voltage-controlled oscillation signal based on the analog and digital control signals, and a signal switch to supply the analog control signal to the integrator in the first mode and to the voltage-controlled oscillator in the second mode.Type: ApplicationFiled: June 22, 2016Publication date: December 29, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Akihide SAI, Hidenori Okuni, Masanori Furuta
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Publication number: 20160377741Abstract: According to an embodiment, a signal processor includes an integrator, a differentiator, a zero cross detector, a pile-up detector, an event interval detector, a counter, and a creator. The integrator is configured to calculate charge of current from a photoelectric converter for an incident radiation. The differentiator is configured to calculate a differential value of the current. The zero cross detector is configured to detect a zero cross of the differential value. The pile-up detector is configured to detect pile-up of the current based on the zero cross. The event interval detector is configured to detect, based on the zero cross and pile-up, an event interval of the radiation entering. The counter is configured to count, based on the charge and pile-up, the respective numbers of events according to the charge and the event interval. The creator is configured to create histograms for the numbers of events.Type: ApplicationFiled: September 8, 2016Publication date: December 29, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hideyuki FUNAKI, Shunsuke KIMURA, Go KAWATA, Tetsuro ITAKURA, Masanori FURUTA
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RADIATION MEASURING APPARATUS, COMPUTER PROGRAM PRODUCT, AND RADIATION COMPUTED TOMOGRAPHY APPARATUS
Publication number: 20160370475Abstract: According to an embodiment, a radiation measuring apparatus includes a detector, comparators, a threshold controller, counters, and a generator. The detector includes plural detecting elements each configured to convert energy of incident radiation into a first electrical signal. The comparators correspond to the respective detecting elements, each comparator being configured to output a second electrical signal when a level of the corresponding first electrical signal is not less than a threshold. The threshold controller is configured to supply a first value as the threshold to the respective comparators at a first time, and supply a second value as the threshold to the respective comparators at a second time. The counters correspond to the respective comparators, each counter being configured to count the corresponding second electrical signal. The generator is configured to generate a pulse height frequency distribution of the radiation by using counts of the counters.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Go KAWATA, Shunsuke Kimura, Hideyuki Funaki, Masanori Furuta, Tetsuro Itakura -
Patent number: 9515684Abstract: According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to-digital converter and an input sensitivity controller. In the voltage controlled oscillator, input sensitivity relative to a baseband signal is controlled based on an input sensitivity control signal. The voltage controlled oscillator oscillates at a frequency controlled by a voltage of the baseband signal to generate an oscillation signal. The frequency-to-digital converter performs frequency-to-digital conversion of the oscillation signal to generate a digital signal. The input sensitivity controller generates the input sensitivity control signal based on the digital signal.Type: GrantFiled: December 16, 2015Date of Patent: December 6, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tuan Thanh Ta, Akihide Sai, Masanori Furuta
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Publication number: 20160349380Abstract: A pulse detection circuit according to an embodiment includes a conversion circuit, a delay circuit, first and second comparators, a latch, and a generation circuit. The conversion circuit converts an input signal into a thermometer code signal. The delay circuit outputs a delay signal being the thermometer code signal delayed by a predetermined delay time. The first comparator (The second comparator) compares the thermometer code signal with the delay signal and outputs an increase signal (a decrease signal) indicating whether the input signal is larger (smaller) than the input signal before the delay time. Based on the increase signal and the decrease signal, the latch outputs an increase-decrease signal indicating whether the input signal is increasing or decreasing. Based on the thermometer code signal and the increase-decrease signal, the generation circuit generates a pulse detection signal and a pileup detection signal.Type: ApplicationFiled: May 26, 2016Publication date: December 1, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hirokatsu SHIRAHAMA, Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki
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Publication number: 20160352349Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.Type: ApplicationFiled: May 25, 2016Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kentaro YOSHIOKA, Masanori FURUTA, Junya MATSUNO, Tetsuro ITAKURA
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Publication number: 20160336930Abstract: An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.Type: ApplicationFiled: April 7, 2016Publication date: November 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junya MATSUNO, Masanori FURUTA, Tetsuro ITAKURA
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Publication number: 20160329881Abstract: An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase. The operational amplifier amplifies and outputs the analog input signal held by the sampling capacitance in the amplifying phase. The feedback capacitance is connected between the input terminal of the operational amplifier and the analog output terminal. The level shift circuit includes a level shift capacitance to sample the analog input signal in the sampling phase. A plurality of level shift capacitances is provided and connected in cascade between the output terminal of the operational amplifier and the analog output terminal.Type: ApplicationFiled: March 4, 2016Publication date: November 10, 2016Applicants: KABUSHIKI KAISHA TOSHIBA, Tokyo University of Science FoundationInventors: Junya MATSUNO, Masanori FURUTA, Tetsuro ITAKURA, Akira HYOGO, Tatsuji MATSUURA, Takuya HARA
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Publication number: 20160274246Abstract: According to an embodiment, a circuit includes a shunt and a controller. The shunt shunts input current into a plurality of current paths. The controller controls a gain of current inputted to the shunt by combining the current that is shunted into the current paths by the shunt in combination corresponding to a first signal from the outside or changing a shunt ratio with which the shunt shunts the current into the current paths corresponding to the first signal.Type: ApplicationFiled: November 20, 2015Publication date: September 22, 2016Inventors: Shunsuke KIMURA, Hirokatsu SHIRAHAMA, Go Kawata, Masanori FURUTA, Hideyuki FUNAKI, Tetsuro ITAKURA
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Publication number: 20160269006Abstract: A waveform shaping filter according to an embodiment includes at least one filter stage and a control circuit. The filter stage includes a differentiation signal generation circuit, a proportional signal generation circuit, and an adder circuit. The differentiation signal generation circuit generates a differentiation signal obtained by amplifying a differentiation component of an input signal. The proportional signal generation circuit generates a proportional signal obtained by amplifying the input signal. The adder circuit outputs an output signal obtained by adding the proportional signal and the differentiation signal. The control circuit compares the output signal and a first detection level, detects at least one of an overshoot and an undershoot of the output signal, and controls a time constant of the filter stage, based on a detection result.Type: ApplicationFiled: February 25, 2016Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Hideyuki FUNAKI, Go KAWATA, Hirokatsu SHIRAHAMA
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Patent number: 9413368Abstract: According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second time shifter. The peak time detector detects, from the digital signal, a first time at which the digital signal exhibits one of a maximal value and a minimal value. The first time shifter adds or subtracts a first natural number multiple of the predetermined period to or from the first time. The zero-crossing time detector detects, from the digital signal, a second time at which the digital signal exhibits one of a positive zero-crossing and a negative zero-crossing. The second time shifter adds or subtracts the first natural number multiple of the predetermined period to or from the second time.Type: GrantFiled: December 18, 2015Date of Patent: August 9, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tuan Thanh Ta, Hidenori Okuni, Akihide Sai, Masanori Furuta
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Patent number: 9407221Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.Type: GrantFiled: October 30, 2014Date of Patent: August 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki
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Publication number: 20160211830Abstract: A waveform shaping filter according to one embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to the one end of the first resistor and an output terminal connected to the control terminal of the first transistor.Type: ApplicationFiled: January 19, 2016Publication date: July 21, 2016Inventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Hideyuki FUNAKI, Go KAWATA, Hirokatsu SHIRAHAMA
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Publication number: 20160182066Abstract: According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second time shifter. The peak time detector detects, from the digital signal, a first time at which the digital signal exhibits one of a maximal value and a minimal value. The first time shifter adds or subtracts a first natural number multiple of the predetermined period to or from the first time. The zero-crossing time detector detects, from the digital signal, a second time at which the digital signal exhibits one of a positive zero-crossing and a negative zero-crossing. The second time shifter adds or subtracts the first natural number multiple of the predetermined period to or from the second time.Type: ApplicationFiled: December 18, 2015Publication date: June 23, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tuan Thanh TA, Hidenori OKUNI, Akihide SAI, Masanori FURUTA
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Publication number: 20160173303Abstract: A wireless communication device has an analog control loop circuitry that generates an analog control signal to adjust a phase of a voltage controlled oscillation signal, in accordance with a phase of a reception signal, a digital control loop circuitry that generates a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and having a phase opposite to a phase of the analog control signal, a voltage controlled oscillator that generates the voltage controlled oscillation signal, on the basis of the analog control signal and the digital control signal, and a data slicer that generates a digital signal obtained by digital demodulation of the reception signal, on the basis of a comparison result of the digital control signal and a predetermined threshold value.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Akihide SAI, Masanori Furuta, Tetsuro Itakura
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Publication number: 20160173137Abstract: According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to--digital converter and an input sensitivity controller. In the voltage controlled oscillator, input sensitivity relative to a baseband signal is controlled based on an input sensitivity control signal. The voltage controlled oscillator oscillates at a frequency controlled by a voltage of the baseband signal to generate an oscillation signal. . The frequency--to-digital converter performs frequency-to-digital conversion of the oscillation signal to generate a digital signal. The input sensitivity controller generates the input sensitivity control signal based on the digital signal.Type: ApplicationFiled: December 16, 2015Publication date: June 16, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tuan Thanh TA, Akihide SAI, Masanori FURUTA
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Patent number: 9369098Abstract: An inverting amplifier according to a first embodiment includes an inverter circuit, a first voltage generating circuit, and a second voltage generating circuit. The inverter circuit has an input terminal, an output terminal, a first first-conductivity transistor, and a first second-conductivity transistor. The first (second) voltage generating circuit has a first (second) current source, a second first (second)-conductivity transistor, and a third first (second)-conductivity transistor. The first (second) current source supplies a predetermined current. The second first (second)-conductivity transistor has a control terminal with a predetermined bias voltage applied, and two ends connected to the other end of the first first (second)-conductivity transistor and the first (second) current source, respectively.Type: GrantFiled: February 12, 2015Date of Patent: June 14, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuro Itakura, Masanori Furuta
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Patent number: 9355283Abstract: An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result.Type: GrantFiled: May 22, 2015Date of Patent: May 31, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Hideyuki Funaki, Go Kawata
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Patent number: 9312873Abstract: An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.Type: GrantFiled: January 5, 2015Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanori Furuta, Kei Shiraishi, Yasuhiro Shinozuka
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Patent number: 9240797Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.Type: GrantFiled: March 13, 2015Date of Patent: January 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kei Shiraishi, Masanori Furuta, Junya Matsuno, Tetsuro Itakura