Patents by Inventor Masanori Miyata
Masanori Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966210Abstract: A substrate processing apparatus includes a device management controller including a parts management control part configured to monitor the state of parts constituting the apparatus, a device state monitoring control part configured to monitor integrity of device data obtained from an operation state of the parts constituting the apparatus, and a data matching control part configured to monitor facility data provided from a factory facility to the apparatus. The device management controller is configured to derive information evaluating the operation state of the apparatus based on a plurality of monitoring result data selected from a group consisting of maintenance timing monitoring result data acquired by the parts management control part, device state monitoring result data acquired by the device state monitoring control part, and utility monitoring result data acquired by the data matching control part.Type: GrantFiled: February 25, 2020Date of Patent: April 23, 2024Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Kazuhide Asai, Kazuyoshi Yamamoto, Hidemoto Hayashihara, Takayuki Kawagishi, Kayoko Yashiki, Yukio Miyata, Hiroyuki Iwakura, Masanori Okuno, Kenichi Fujimoto, Ryuichi Kaji
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Publication number: 20230037409Abstract: In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×1012 cm?2 or less.Type: ApplicationFiled: October 25, 2022Publication date: February 9, 2023Inventors: Masanori MIYATA, Shuji YONEDA, Masaru SENOO, Yuki YAKUSHIGAWA
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Publication number: 20220181471Abstract: A semiconductor device includes an IGBT region in which an IGBT element is formed and an FWD region in which an FWD element is formed. The IGBT region includes a first region and a second region different from the first region. The FWD region and the first region of the IGBT region have a carrier extraction portion that facilitates extraction of carriers injected from a second electrode compared to the second region when a forward bias for causing the FWD element to operate as a diode is applied between a first electrode and the second electrode.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Inventors: MASANORI MIYATA, YUUMA KAGATA, YUKI YAKUSHIGAWA, MASARU SENOO, HIROSHI HOSOKAWA, TAKAYA NAGAI
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Publication number: 20210217845Abstract: A semiconductor device has a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, a collector layer, a field stop layer, a first electrode and a second electrode. The base layer is disposed on the drift layer. The emitter region is disposed on a surface layer portion of the base layer. The gate insulation film is disposed between the drift layer and the emitter layer. The gate electrode is disposed on the gate insulation film. The collector layer is disposed at a portion of the drift layer opposite to the base layer. The field stop layer is disposed between the collector layer and the drift layer. The field stop layer has a higher carrier concentration than the drift layer. The first electrode is electrically connected to the base layer and the emitter region. The second electrode is electrically connected to the collector layer.Type: ApplicationFiled: March 11, 2021Publication date: July 15, 2021Inventors: MASANORI MIYATA, SHUJI YONEDA, YUKI YAKUSHIGAWA, MASARU SENOO
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Patent number: 10748988Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.Type: GrantFiled: July 8, 2019Date of Patent: August 18, 2020Assignee: DENSO CORPORATIONInventors: Masanori Miyata, Shigeki Takahashi, Masakiyo Sumitomo, Tomofusa Shiga
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Publication number: 20190333987Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventors: Masanori MIYATA, Shigeki TAKAHASHI, Masakiyo SUMITOMO, Tomofusa SHIGA
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Patent number: 10365317Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.Type: GrantFiled: June 9, 2016Date of Patent: July 30, 2019Assignee: DENSO CORPORATIONInventors: Masanori Miyata, Yoshifumi Okabe
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Patent number: 10163890Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.Type: GrantFiled: January 11, 2018Date of Patent: December 25, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaru Senoo, Masanori Miyata
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Publication number: 20180240792Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.Type: ApplicationFiled: January 11, 2018Publication date: August 23, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaru SENOO, Masanori MIYATA
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Publication number: 20180172752Abstract: A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.Type: ApplicationFiled: June 9, 2016Publication date: June 21, 2018Inventors: Masanori MIYATA, Yoshifumi OKABE
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Patent number: 9863999Abstract: A circuit for inspecting a semiconductor device includes: the semiconductor device that is an object to be inspected and includes a diode; a protection element that is connected in series with the semiconductor device and includes a protection diode having higher breakdown resistance than the diode; a switch that includes a switching element connected in series with the semiconductor device and the protection element; and a coil that provides a loop path together with the semiconductor device and the protection element when the switching element is turned off. Even when the semiconductor device including the diode is broken, an inspection device is restricted from being damaged.Type: GrantFiled: June 23, 2015Date of Patent: January 9, 2018Assignee: DENSO CORPORATIONInventors: Masanori Miyata, Takafumi Arakawa
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Publication number: 20170131344Abstract: A circuit for inspecting a semiconductor device includes: the semiconductor device that is an object to be inspected and includes a diode; a protection element that is connected in series with the semiconductor device and includes a protection diode having higher breakdown resistance than the diode; a switch that includes a switching element connected in series with the semiconductor device and the protection element; and a coil that provides a loop path together with the semiconductor device and the protection element when the switching element is turned off. Even when the semiconductor device including the diode is broken, an inspection device is restricted from being damaged.Type: ApplicationFiled: June 23, 2015Publication date: May 11, 2017Applicant: DENSO CORPORATIONInventors: Masanori MIYATA, Takafumi ARAKAWA
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Patent number: 8450858Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.Type: GrantFiled: April 30, 2010Date of Patent: May 28, 2013Assignee: Ricoh Company, Ltd.Inventors: Takuya Takahashi, Fumihiro Fuchino, Yuuichi Kohno, Masanori Miyata
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Patent number: 8116894Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .Type: GrantFiled: December 19, 2008Date of Patent: February 14, 2012Assignee: Ricoh Company, Ltd.Inventors: Masanori Miyata, Taro Usami, Koichi Sogawa, Kenji Nishihara, Tadao Uehara, Shisyo Chin, Hiroaki Teratani, Akinori Suzuki, Yuuichi Kohno, Tetsuya Okada, Tohru Haruki
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Publication number: 20100295184Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.Type: ApplicationFiled: April 30, 2010Publication date: November 25, 2010Applicant: RICOH COMPANY, LTD.Inventors: Takuya Takahashi, Fumihiro Fuchino, Yuuichi Kohno, Masanori Miyata
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Patent number: 7723826Abstract: A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view.Type: GrantFiled: September 17, 2008Date of Patent: May 25, 2010Assignee: Ricoh Company, Ltd.Inventors: Masanori Miyata, Hidetsugu Miyake, Tadao Uehara, Fumihiro Fuchino, Mikinori Oguni, Akira Washino
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Publication number: 20090170323Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Inventors: MASANORI MIYATA, Taro Usami, Koichi Sogawa, Kenji Nishihara, Tadao Uehara, Shisyo Chin, Hiroaki Teratani, Akinori Suzuki, Yuuichi Kohno, Tetsuya Okada, Tohru Haruki
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Publication number: 20090079095Abstract: A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view.Type: ApplicationFiled: September 17, 2008Publication date: March 26, 2009Inventors: Masanori Miyata, Hidetsugu Miyake, Tadao Uehara, Fumihiro Fuchino, Mikinori Oguni, Akira Washino
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Patent number: 7464048Abstract: There is disclosed an invention for generating contract information for an image forming apparatus for which the user is going to conclude a contract. The history information of an image forming apparatus used by the user and having a contract history is stored and managed in correlation with the user. Such management is executed in a center server capable communication with the image forming apparatus through a predetermined communication channel. The above-mentioned information includes contract term, machine type, number of print outputs etc. of the image forming apparatus. Also the image forming apparatus to be managed includes that currently contracted and that contracted in the past. In case the user wishes to conclude a new contract for an image forming apparatus, new contract information is generated according to the history information managed by the center server in correlation with the user. This invention provides a system capable of realizing the foregoing.Type: GrantFiled: February 9, 2001Date of Patent: December 9, 2008Assignee: Canon Kabushiki KaishaInventors: Hiroaki Ishii, Toshio Honma, Shigeru Ueda, Hironobu Araki, Yoshinori Ikeda, Naoji Hayakawa, Masanori Miyata, Hiroshi Omura, Hirokazu Uchio, Kengo Kawamoto
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Publication number: 20010034745Abstract: There is disclosed an invention for generating contract information for an image forming apparatus for which the user is going to conclude a contract. The history information of an image forming apparatus used by the user and having a contract history is stored and managed in correlation with the user. Such management is executed in a center server capable communication with the image forming apparatus through a predetermined communication channel. The above-mentioned information includes contract term, machine type, number of print outputs etc. of the image forming apparatus. Also the image forming apparatus to be managed includes that currently contracted and that contracted in the past. In case the user wishes to conclude a new contract for an image forming apparatus, new contract information is generated according to the history information managed by the center server in correlation with the user. This invention provides a system capable of realizing the foregoing.Type: ApplicationFiled: February 9, 2001Publication date: October 25, 2001Inventors: Hiroaki Ishii, Toshio Honma, Shigeru Ueda, Hironobu Araki, Yoshinori Ikeda, Naoji Hayakawa, Masanori Miyata, Hiroshi Omura, Hirokazu Uchio, Kengo Kawamoto