Patents by Inventor Masanori Tsutsumi

Masanori Tsutsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957680
    Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 23, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Masanori Tsutsumi, Sayako Nagamine, Yuji Fukano, Akio Nishida, Christopher J. Petti
  • Patent number: 10903222
    Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 26, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Masaaki Higashitani, Masanori Tsutsumi, Zhixin Cui
  • Patent number: 10903232
    Abstract: Laterally alternating sequences of memory opening fill structures and isolation dielectric pillars are formed between alternating stacks of insulating layers and sacrificial material layers. Each of the memory opening fill structures includes, from inside to outside, a vertical semiconductor channel, a tunneling dielectric layer, and an aluminum oxide liner. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers. Discrete silicon nitride portions are formed on physically exposed surfaces of the aluminum oxide liners employing a selective silicon nitride deposition process, and are employed as charge storage elements. Electrically conductive layers are formed in remaining volumes of the backside recesses. The silicon nitride portions are formed as a pair of discrete silicon nitride portions at each level of the electrically conductive layers within each memory opening fill structure.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: January 26, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Masanori Tsutsumi
  • Patent number: 10861869
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 8, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ryo Nakamura, Yu Ueda, Tatsuya Hinoue, Shigehisa Inoue, Genta Mizuno, Masanori Tsutsumi
  • Patent number: 10748925
    Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 18, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Manabu Kakazu, Raghuveer S. Makala, Senaka Kanakamedala
  • Patent number: 10748927
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 18, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Shigehisa Inoue, Tomohiro Kubo, James Kai
  • Publication number: 20200251489
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.
    Type: Application
    Filed: July 23, 2019
    Publication date: August 6, 2020
    Inventors: Masanori TSUTSUMI, Shigehisa INOUE, Tomohiro KUBO, James KAI
  • Publication number: 20200251486
    Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Masanori TSUTSUMI, Manabu KAKAZU, Raghuveer S. MAKALA, Senaka KANAKAMEDALA
  • Publication number: 20200251479
    Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 6, 2020
    Inventors: Kiyohiko SAKAKIBARA, Masaaki HIGASHITANI, Masanori TSUTSUMI, Zhixin CUI
  • Publication number: 20200227397
    Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Shinsuke YADA, Masanori TSUTSUMI, Sayako NAGAMINE, Yuji FUKANO, Akio NISHIDA, Christopher J. PETTI
  • Patent number: 10559582
    Abstract: A three-dimensional memory device includes source-level material layers located over a substrate, the source-level material layers containing a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the substrate-level material layers, memory stack structures extending through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel having a bottom surface that contacts a respective horizontal surface of the source contact layer, and dielectric pillar structures embedded within the substrate-level material layers and located between the memory stack structures.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: February 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Shinsuke Yada, Masanori Tsutsumi
  • Publication number: 20200020715
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: January 16, 2020
    Inventors: Ryo NAKAMURA, Yu UEDA, Tatsuya HINOUE, Shigehisa INOUE, Genta MIZUNO, Masanori TSUTSUMI
  • Publication number: 20190371807
    Abstract: A three-dimensional memory device includes source-level material layers located over a substrate, the source-level material layers containing a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the substrate-level material layers, memory stack structures extending through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel having a bottom surface that contacts a respective horizontal surface of the source contact layer, and dielectric pillar structures embedded within the substrate-level material layers and located between the memory stack structures.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Masatoshi NISHIKAWA, Shinsuke YADA, Masanori TSUTSUMI
  • Patent number: 10453798
    Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda
  • Publication number: 20190252405
    Abstract: Laterally alternating sequences of memory opening fill structures and isolation dielectric pillars are formed between alternating stacks of insulating layers and sacrificial material layers. Each of the memory opening fill structures includes, from inside to outside, a vertical semiconductor channel, a tunneling dielectric layer, and an aluminum oxide liner. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers. Discrete silicon nitride portions are formed on physically exposed surfaces of the aluminum oxide liners employing a selective silicon nitride deposition process, and are employed as charge storage elements. Electrically conductive layers are formed in remaining volumes of the backside recesses. The silicon nitride portions are formed as a pair of discrete silicon nitride portions at each level of the electrically conductive layers within each memory opening fill structure.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 15, 2019
    Inventor: Masanori TSUTSUMI
  • Publication number: 20190096808
    Abstract: A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA
  • Patent number: 10236300
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Masanori Tsutsumi, Shinsuke Yada, Sayako Nagamine, Johann Alsmeier
  • Publication number: 20190035803
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Application
    Filed: October 16, 2017
    Publication date: January 31, 2019
    Inventors: Yanli ZHANG, Masanori TSUTSUMI, Shinsuke YADA, Sayako NAGAMINE, Johann ALSMEIER
  • Patent number: 10192878
    Abstract: Sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Shinsuke Yada, Yanli Zhang
  • Publication number: 20180342531
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.
    Type: Application
    Filed: May 29, 2017
    Publication date: November 29, 2018
    Inventors: Hiromasa Susuki, Masanori Tsutsumi, Shigehisa Inoue, Junji Oh, Kensuke Yamaguchi, Seiji Shimabukuro, Yuji Fukano, Ryoichi Ehara, Youko Furihata