Patents by Inventor Masanori Uchida

Masanori Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200009490
    Abstract: An object of the present invention is to provide a dust collector including a pulse jet type dust removal mechanism capable of uniformly removing dust over the entire length of a cylindrical filter without increasing the pressure loss of the cylindrical filter; and a dust removal method for such a dust collector.
    Type: Application
    Filed: December 12, 2017
    Publication date: January 9, 2020
    Inventors: Takashi SUZUKI, Hiroyuki Amano, Kazuhiko Kitahora, Masanori Uchida, Koh Saito
  • Publication number: 20160331015
    Abstract: A natural yeast extract which is rich in glutamic acid and therefore has an impact at first taste. Further, provided is a yeast extract which is also rich in 5?-guanylic acid or 5?-inosinic acid and therefore has strong umami. Further, provided is a yeast mutant capable of accumulating a large amount of glutamic acid, glutamine and ribonucleic acid for obtaining such a yeast extract. A yeast mutant to which resistance to organic acids and analogues thereof has been imparted by inducing spontaneous mutation, accumulates a significant amount, i.e., 10% by weight or more of the total of free glutamic acid and glutamine in the cell, and further accumulates 5% by weight or more of a ribonucleic acid. The yeast extract produced by using this strain contains 20% by weight or more of L-glutamic acid, and further contains 3% by weight or more of 5?-IG.
    Type: Application
    Filed: July 5, 2016
    Publication date: November 17, 2016
    Inventors: Ryo IWAKIRI, Hirokazu MAEKAWA, Naohisa MASUO, Shogo FURUE, Hiroko KODERA, Setsuko HIRAKURA, Masahiro NISHIDA, Masanori UCHIDA, Sakiko IKEDA
  • Publication number: 20150225690
    Abstract: A natural yeast extract which is rich in glutamic acid and therefore has an impact at first taste. Further, provided is a yeast extract which is also rich in 5?-guanylic acid or 5?-inosinic acid and therefore has strong umami. Further, provided is a yeast mutant capable of accumulating a large amount of glutamic acid, glutamine and ribonucleic acid for obtaining such a yeast extract. A yeast mutant to which resistance to organic acids and analogues thereof has been imparted by inducing spontaneous mutation, accumulates a significant amount, i.e., 10% by weight or more of the total of free glutamic acid and glutamine in the cell, and further accumulates 5% by weight or more of a ribonucleic acid. The yeast extract produced by using this strain contains 20% by weight or more of L-glutamic acid, and further contains 3% by weight or more of 5?-IG.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Ryo IWAKIRI, Hirokazu MAEKAWA, Naohisa MASUO, Shogo FURUE, Hiroko KODERA, Setsuko HIRAKURA, Masahiro NISHIDA, Masanori UCHIDA, Sakiko IKEDA
  • Patent number: 9084435
    Abstract: The present invention provides a natural yeast extract having a high-impact first taste by containing glutamic acid in a large amount. Further, the present invention provides a yeast extract having strong umami by containing 5?-guanylic acid or 5?-inosinic acid in a large amount. In addition, the present invention provides a yeast mutant accumulating glutamic acid, glutamine, and ribonucleic acid in a large amount for obtaining the yeast extract. A yeast mutant inducing a natural mutation to which organic acid-tolerance or organic acid analogue-tolerance is imparted accumulates free glutamic acid and glutamine in such a significant amount as a total amount of 10% by weight or more in a cell, and further accumulates ribonucleic acid in an amount of 5% by weight or more. A yeast extract produced using the above yeast mutant contains L-glutamic acid in an amount of 20% by weight or more, and further contains 5?-IG in an amount of 3% by weight or more.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: July 21, 2015
    Assignee: KOHJIN CO., LTD.
    Inventors: Ryo Iwakiri, Hirokazu Maekawa, Naohisa Masuo, Shogo Furue, Hiroko Kodera, Setsuko Hirakura, Masahiro Nishida, Masanori Uchida, Sakiko Ikeda
  • Patent number: 8679973
    Abstract: The method of manufacturing the semiconductor device comprises forming a transistor including a gate electrode and a source/drain diffused layer over a semiconductor substrate, forming a nickel platinum film over the semiconductor substrate, covering the gate electrode and the source/drain diffused layer, making a first thermal processing to react the nickel platinum film with the source/drain diffused layer to form a nickel platinum silicide film, and removing an unreacted part of the nickel platinum film using a chemical liquid of 71° C. or more containing hydrogen peroxide.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Masanori Uchida
  • Publication number: 20120171864
    Abstract: The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16, forming a NiPt film 28 over the silicon substrate 10, covering the gate electrode 16 and the source/drain diffused layers 26, making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34a, 34b on the source/drain diffused layers 24, and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34a, 34b.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Masanori UCHIDA
  • Patent number: 8008194
    Abstract: The semiconductor manufacturing method comprises the step of forming a metal alloy film of an alloy of a metal of Ni or others and a noble metal over a semiconductor substrate containing a region where silicon is partially exposed; the step of selectively reacting the silicon in the region and the metal alloy film by thermal processing to form metal silicide film containing the metal of Ni or others and the noble metal on the region; and the step of removing the metal alloy film remaining unreacted by using a solution containing hydrogen peroxide with a transition metal, which has higher ionization tendency than the metal of Ni or others, dissolved in.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: August 30, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masanori Uchida
  • Publication number: 20110020528
    Abstract: A natural yeast extract which is rich in glutamic acid and therefore has an impact at first taste. Further, provided is a yeast extract which is also rich in 5?-guanylic acid or 5?-inosinic acid and therefore has strong umami. Further, provided is a yeast mutant capable of accumulating a large amount of glutamic acid, glutamine and ribonucleic acid for obtaining such a yeast extract. A yeast mutant to which resistance to organic acids and analogues thereof has been imparted by inducing spontaneous mutation, accumulates a significant amount, i.e., 10% by weight or more of the total of free glutamic acid and glutamine in the cell, and further accumulates 5% by weight or more of a ribonucleic acid. The yeast extract produced by using this strain contains 20% by weight or more of L-glutamic acid, and further contains 3% by weight or more of 5?-IG.
    Type: Application
    Filed: March 26, 2009
    Publication date: January 27, 2011
    Applicant: KOHJIN CO., LTD.
    Inventors: Ryo Iwakiri, Hirokazu Maekawa, Naohisa Masuo, Shogo Furue, Hiroko Kodera, Setsuko Hirakura, Masahiro Nishida, Masanori Uchida, Sakiko Ikeda
  • Publication number: 20080220602
    Abstract: The semiconductor manufacturing method comprises the step of forming a metal alloy film of an alloy of a metal of Ni or others and a noble metal over a semiconductor substrate containing a region where silicon is partially exposed; the step of selectively reacting the silicon in the region and the metal alloy film by thermal processing to form metal silicide film containing the metal of Ni or others and the noble metal on the region; and the step of removing the metal alloy film remaining unreacted by using a solution containing hydrogen peroxide with a transition metal, which has higher ionization tendency than the metal of Ni or others, dissolved in.
    Type: Application
    Filed: July 31, 2007
    Publication date: September 11, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Masanori UCHIDA
  • Publication number: 20080090369
    Abstract: The method of manufacturing the semiconductor device comprises forming a transistor including a gate electrode and a source/drain diffused layer over a semiconductor substrate, forming a nickel platinum film over the semiconductor substrate, covering the gate electrode and the source/drain diffused layer, making a first thermal processing to react the nickel platinum film with the source/drain diffused layer to form a nickel platinum silicide film, and removing an unreacted part of the nickel platinum film using a chemical liquid of 71° C. or more containing hydrogen peroxide.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 17, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Masanori UCHIDA
  • Publication number: 20060085508
    Abstract: An E-mail communication apparatus that edits files attached to an E-mail and transmits the E-mail. The apparatus comprises a mail generating unit, a temporary-file generating unit, a temporary-file editing unit, an attached-file updating unit, and a transmitting unit. The mail generating unit generates a mail which is to be transmitted and to which a file is attached. The temporary-file generating unit generates a temporary file by copying the file attached to the mail that is to be transmitted. The temporary-file editing unit calls an application associated with the file attached to the mail that is to be transmitted, edits the temporary file and updates the temporary file. The attached-file updating unit replaces the file attached to the mail that is to be transmitted, with the temporary file copied. The transmitting unit transmits the mail to be transmitted.
    Type: Application
    Filed: January 18, 2005
    Publication date: April 20, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masanori Uchida, Masayoshi Tanigawa
  • Publication number: 20050086194
    Abstract: An information reference apparatus includes: a reference information storage part storing predetermined reference information; a reference range defining information storage part storing predetermined reference range defining information; and a reference range defining part referring to the reference range defining information stored for a user by the reference range defining information storage part and defining a range of the reference information stored by the reference information storage part, in which range the reference information is available for the user to refer to.
    Type: Application
    Filed: March 1, 2004
    Publication date: April 21, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Shigehiko Suzuki, Masanori Uchida, Yasunori Ushio
  • Patent number: 5498978
    Abstract: A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . .
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: March 12, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Takahashi, Fumitoshi Hatori, Kazutaka Nogami, Masanori Uchida
  • Patent number: 5396448
    Abstract: The associative memory capable of improving the efficiency in replacing an entry and testability of compare operation. The associative memory includes a Content Addressable Memory (CAM) cell array for executing a compare operation; a Random Access Memory (RAM) cell array for operating responsive to a result of the CAM cell array; and a HIT entry number detection circuit for receiving a result of the compare operation in the CAM cell array and outputting a HIT entry number.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshinari Takayanagi, Masanori Uchida
  • Patent number: 5294911
    Abstract: According to this invention, a bit data comparing section has a plurality of groups each having a plurality of bit comparators. Each of the plurality of bit comparators compares one bit of address data input to the bit comparator with bit data stored in the bit comparator in advance and outputs a comparison result. Output data from a plurality of bit comparators belonging to one group are unified by one subsense line belonging to the group and input to a control terminal of a switching element. The switching element performs a switching operation in accordance with the input data. A main sense line is connected to the switching element, and a load circuit is connected between the main sense line and a power supply terminal.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: March 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Uchida, Takayasu Sakurai
  • Patent number: 5293515
    Abstract: An amplifier circuit includes two inverter circuits. Each inverter circuit provides an output signal in response to a respective input signal. The inverter circuits are supplied with a power source voltage through a MOS transistor circuit. The MOS transistor circuit includes two MOS transistors each having gate electrodes supplied with the output of the inverter circuits.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: March 8, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Uchida, Tetsuya Iizuka
  • Patent number: D885519
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 26, 2020
    Assignee: SINTOKOGIO, LTD.
    Inventors: Takashi Suzuki, Hiroyuki Amano, Masanori Uchida, Koh Saito