Patents by Inventor Masao Iwase
Masao Iwase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230088310Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 11552095Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 26, 2021Date of Patent: January 10, 2023Assignee: KIOXIA CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20210217755Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: July 15, 2021Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10971511Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: March 11, 2020Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20200212053Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10622372Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: January 30, 2019Date of Patent: April 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20190164979Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: January 30, 2019Publication date: May 30, 2019Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10199387Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: August 17, 2018Date of Patent: February 5, 2019Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20180358368Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: August 17, 2018Publication date: December 13, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 10056403Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 18, 2017Date of Patent: August 21, 2018Assignee: Toshiba Memory CorporationInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20180006042Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 9768188Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: November 11, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20170062441Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 9502299Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 2, 2014Date of Patent: November 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20160079266Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a selection gate electrode, a semiconductor pillar, a first insulating member, a second insulating member, a third insulating member. The stacked body is provided on the substrate. The selection gate electrode is provided on the stacked body. The first insulating member divides the stacked body in a first direction. The second insulating member is provided in an area directly above the first insulating member and dividing the selection gate electrode in the first direction. The third insulating member is provided in a region other than the area directly above the first insulating member and dividing the selection gate electrode in the first direction. An average width of the second insulating member in the first direction is larger than an average width of the third insulating member in the first direction.Type: ApplicationFiled: March 13, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Nozomi KIDO, Masao IWASE, Tadashi IGUCHI
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Publication number: 20150263024Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 8786003Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.Type: GrantFiled: March 15, 2012Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masao Iwase, Hiroyasu Tanaka
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Patent number: 8735246Abstract: According to one embodiment, a method is disclosed for manufacturing nonvolatile semiconductor memory device including forming a stacked body by alternately stacking an electrode layer and a layer-to-be-etched, and forming an oxidized layer between the layer-to-be-etched provided at least in any side of an upper side and a lower side of the electrode layer and the electrode layer. The method can include forming a groove which passes through the stacked body. The method can include embedding an insulating body within the groove. The method can include forming a hole which passes through the stacked body. The method can include selectively removing the layer-to-be-etched via the hole. The method can include forming a charge storage layer in an inner side of the hole. The method can include forming a channel body layer in an inner side of the charge storage layer.Type: GrantFiled: August 31, 2012Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Kuboi, Tadashi Iguchi, Masao Iwase, Toru Matsuda
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Publication number: 20130228841Abstract: According to one embodiment, a method is disclosed for manufacturing nonvolatile semiconductor memory device including forming a stacked body by alternately stacking an electrode layer and a layer-to-be-etched, and forming an oxidized layer between the layer-to-be-etched provided at least in any side of an upper side and a lower side of the electrode layer and the electrode layer. The method can include forming a groove which passes through the stacked body. The method can include embedding an insulating body within the groove. The method can include forming a hole which passes through the stacked body. The method can include selectively removing the layer-to-be-etched via the hole. The method can include forming a charge storage layer in an inner side of the hole. The method can include forming a channel body layer in an inner side of the charge storage layer.Type: ApplicationFiled: August 31, 2012Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Shuichi KUBOI, Tadashi Iguchi, Masao Iwase, Toru Matsuda
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Publication number: 20130056816Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.Type: ApplicationFiled: March 15, 2012Publication date: March 7, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Masao Iwase, Hiroyasu Tanaka