Abstract: A shift register circuit for converting a form of a datum with N bits comprises a shift register with a bit capacity of at least N+1 bits. Each bit of the shift register is set so as to become a predetermined logic condition by a setting means. At this time, the supply of shift pulses to the shift register is begun, so that the data in the shift register is shifted and predetermined data are input in sequence. A detecting means detects whether or not the shift register has carried out the shift operations by the predetermined times on the basis of the logical condition of the predetermined bit or bits in the shift register. When the detecting means detects that the shift operations have been carried out by the predetermined times, the supply of the shift pulses to the shift register is stopped. This shift register circuit can be used for a parallel to serial converter or a serial to parallel converter.

Abstract: An offset compensating circuit is disclosed. The offset compensating circuit is inserted in a negative feedback loop of a circuit to be compensated and includes an integration circuit. The integration circuit includes a switching means mechanism and a switched capacitor type integrator. Said switching means mechanism produces either a positive reference voltage or a negative reference voltage in accordance with the polarity of the output signal of the circuit to be compensated. The positive or negative reference voltage is applied to the switched capacitor type integrator, which produces a compensating voltage signal to be combined with the input signal of the circuit to be compensated.

Abstract: A codec, utilized for an PCM transmission system, has an a/d and d/a converter, and a digital phase locked loop circuit. The digital phase locked loop circuit generates internal operation clocks, which are used for the a/d and d/a converting operations, by dividing the frequency of the applied external clocks by a value determined in accordance with the frequency ratio between frame pulses and the external clocks.

Abstract: A digital-to-analog converter of the capacitive voltage divider type, which comprises an output conductor, a ground conductor, a power source conductor, an array of capacitors and an array of switches connected between said output conductor and either the ground conductor or the power source conductor, and which provides a high impedance element connected between said output conductor and the ground conductor.

Abstract: An asynchronous signal processing circuit device having an A-D converter and a D-A converter in which a single ladder voltage generating circuit is commonly or jointly used by changing over a multiplexer during both the A-D and the D-A conversion processing. The asynchronous signal processing circuit device according to the present invention further comprises an interrupt signal generating circuit which produces an inhibit signal so as to provide a predetermined inhibit period during which the interruption by the second signal processing circuit to the first signal processing circuit is inhibited, thus preventing a misoperation of the asynchronous signal processing circuit device at the time of switching over the converters.