Patents by Inventor Masaru Fukuchi

Masaru Fukuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8739401
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 3, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Patent number: 8742554
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 3, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Patent number: 8420446
    Abstract: A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: April 16, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shimazaki Yo, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20110117704
    Abstract: A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20100325885
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20090146280
    Abstract: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 11, 2009
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20090039486
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Application
    Filed: April 26, 2006
    Publication date: February 12, 2009
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa