Patents by Inventor Masaru Katagiri

Masaru Katagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit devices with protective means against overvoltages
    Patent number: 4509067
    Abstract: An additional N.sup.+ region is provided in a P type substrate adjacent to a protective N.sup.+ resistor region with an insulating layer and metal layer interposed between the N.sup.+ region and the N.sup.+ resistor region. The N.sup.+ resistor region, the oxide layer, the polysilicon layer and N.sup.+ region constitute an MOS transistor, respectively corresponding to a drain region, a gate insulating layer, a gate electrode and a source region of the MOS transistor. When a very high excessive voltage that otherwise would destroy the PN junction between the substrate and the resistor region is applied to the input terminal, the MOS transistor is rendered conductive and the excessive voltage is absorbed.
    Type: Grant
    Filed: March 3, 1982
    Date of Patent: April 2, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Minami, Masaru Katagiri, Hideo Noguchi