Patents by Inventor Masaru Kikuchi

Masaru Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11454836
    Abstract: A laser processing apparatus disclosed in the present application includes: an optical deflection unit capable of changing a deflection direction of and outgoing energy of an incoming laser pulse by changes of a frequency of and an amplitude of a driving signal to be supplied; and a control unit configured to supply driving signals with amplitudes corresponding to respective frequencies. In a laser processing apparatus configured to process a workpiece by leading outgoing laser pulse of the optical deflection unit to the workpiece and irradiating the workpiece with the laser pulse, as the amplitude corresponding to each of the frequencies, the control unit supplies an amplitude having the ratio that is close to the lowest ratio among ratios of the outgoing energy with respect to the incoming energy of the laser pulse at an amplitude having the largest outgoing energy of the optical deflection unit.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 27, 2022
    Assignee: VIA MECHANICS, LTD.
    Inventors: Kazuya Matsumoto, Kazuo Watanabe, Atsushi Sakamoto, Masanori Sato, Mitsuru Kato, Masaru Kikuchi
  • Patent number: 11146752
    Abstract: A solid-state imaging apparatus includes: a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix form, and a plurality of systematic pixel drive lines to transmit drive signals to read out signals from the pixels are arranged for each pixel row; and a row scanning section to simultaneously output the drive signals through the plurality of systematic pixel drive lines to a plurality of pixel rows for different pixel columns.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 12, 2021
    Assignee: Sony Corporation
    Inventors: Yuichiro Araki, Masaru Kikuchi
  • Publication number: 20200004057
    Abstract: A laser processing apparatus disclosed in the present application includes: an optical deflection unit capable of changing a deflection direction of and outgoing energy of an incoming laser pulse by changes of a frequency of and an amplitude of a driving signal to be supplied; and a control unit configured to supply driving signals with amplitudes corresponding to respective frequencies. In a laser processing apparatus configured to process a workpiece by leading outgoing laser pulse of the optical deflection unit to the workpiece and irradiating the workpiece with the laser pulse, as the amplitude corresponding to each of the frequencies, the control unit supplies an amplitude having the ratio that is close to the lowest ratio among ratios of the outgoing energy with respect to the incoming energy of the laser pulse at an amplitude having the largest outgoing energy of the optical deflection unit.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Applicant: Via Mechanics, Ltd.
    Inventors: Kazuya MATSUMOTO, Kazuo WATANABE, Atsushi SAKAMOTO, Masanori SATO, Mitsuru KATO, Masaru KIKUCHI
  • Publication number: 20190110011
    Abstract: A solid-state imaging apparatus includes: a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix form, and a plurality of systematic pixel drive lines to transmit drive signals to read out signals from the pixels are arranged for each pixel row; and a row scanning section to simultaneously output the drive signals through the plurality of systematic pixel drive lines to a plurality of pixel rows for different pixel columns.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 11, 2019
    Inventors: YUICHIRO ARAKI, MASARU KIKUCHI
  • Patent number: 9077919
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: July 7, 2015
    Assignee: SONY CORPORATION
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Publication number: 20140211055
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: Sony Corporation
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Patent number: 8743254
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage VX are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage VX, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Publication number: 20140014823
    Abstract: A solid-state imaging apparatus includes: a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix form, and a plurality of systematic pixel drive lines to transmit drive signals to read out signals from the pixels are arranged for each pixel row; and a row scanning section to simultaneously output the drive signals through the plurality of systematic pixel drive lines to a plurality of pixel rows for different pixel columns.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 16, 2014
    Applicant: SONY CORPORATION
    Inventors: Yuichiro Araki, Masaru Kikuchi
  • Patent number: 8629935
    Abstract: A solid-state imaging device includes plural photoelectric conversion means arranged along light receiving surfaces, readout means for reading out signal charge generated in the photoelectric conversion means, a voltage supply means for supplying various levels of voltages to respective units including the photoelectric conversion means and the readout means, a detection means for detecting level change of a prescribed supply voltage in supply voltages by the voltage supply means and a control means for controlling so that the level change is converged when level change of the prescribed supply voltage is detected by the detection means.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventors: Masaru Kikuchi, Hayato Wakabayashi
  • Patent number: 8599279
    Abstract: A solid-state imaging apparatus includes a comparator for comparing a pixel signal obtained by a pixel section and a reference signal the value of which varies in a stepwise manner, an analog-digital converter for outputting, as a digital value, the amount of time when the pixel signal and the reference signal change levels by the comparator; a reset signal generator for generating a reset signal that triggers a reset operation to be input to the comparator in order to adjust the reference in the analog-digital converter, and a waveform processor provided between the reset signal generator and the comparator for increasing the degree of dullness of a waveform of the reset signal.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventors: Yuuki Yamagata, Ken Koseki, Masaru Kikuchi, Yoshiaki Inada, Junichi Inutsuka, Akari Tajima
  • Publication number: 20130293754
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage VX are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage VX, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Patent number: 8570416
    Abstract: A solid-state imaging apparatus includes: a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix form, and a plurality of systematic pixel drive lines to transmit drive signals to read out signals from the pixels are arranged for each pixel row; and a row scanning section to simultaneously output the drive signals through the plurality of systematic pixel drive lines to a plurality of pixel rows for different pixel columns.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: October 29, 2013
    Assignee: Sony Corporation
    Inventors: Yuichiro Araki, Masaru Kikuchi
  • Patent number: 8502578
    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: August 6, 2013
    Assignee: Sony Corporation
    Inventors: Masahiro Hatano, Masaru Kikuchi
  • Patent number: 8502899
    Abstract: In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become ?W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 6, 2013
    Assignee: Sony Corporation
    Inventors: Hayato Wakabayashi, Masaru Kikuchi, Hiroshi Iwasa, Yuuki Yamagata
  • Patent number: 8471615
    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 25, 2013
    Assignee: Sony Corporation
    Inventors: Masahiro Hatano, Masaru Kikuchi
  • Patent number: 8373477
    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 12, 2013
    Assignee: Sony Corporation
    Inventors: Masahiro Hatano, Masaru Kikuchi
  • Publication number: 20120086839
    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: Sony Corporation
    Inventors: Masahiro Hatano, Masaru Kikuchi
  • Patent number: 8093934
    Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: January 10, 2012
    Assignee: Sony Corporation
    Inventors: Masahiro Hatano, Masaru Kikuchi
  • Publication number: 20120001057
    Abstract: A solid-state imaging apparatus includes a comparator for comparing a pixel signal obtained by a pixel section and a reference signal the value of which varies in a stepwise manner, an analog-digital converter for outputting, as a digital value, the amount of time when the pixel signal and the reference signal change levels by the comparator; a reset signal generator for generating a reset signal that triggers a reset operation to be input to the comparator in order to adjust the reference in the analog-digital converter, and a waveform processor provided between the reset signal generator and the comparator for increasing the degree of dullness of a waveform of the reset signal.
    Type: Application
    Filed: September 14, 2011
    Publication date: January 5, 2012
    Applicant: SONY CORPORATION
    Inventors: Yuuki Yamagata, Ken Koseki, Masaru Kikuchi, Yoshiaki Inada, Junichi Inutsuka, Akari Tajima
  • Patent number: 8035696
    Abstract: A solid-state imaging apparatus includes comparing means for comparing a pixel signal obtained by a pixel section and a reference signal the value of which varies in a stepwise manner, analog-digital converting means for outputting, as a digital value, the amount of time when the pixel signal and the reference signal change levels by the comparing means, reset signal generating means for generating a reset signal that triggers a reset operation to be input to the comparing means in order to adjust the reference in the analog-digital converting means, and waveform processing means provided between the reset signal generating means and the comparing means for increasing the degree of dullness of a waveform of the reset signal.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: October 11, 2011
    Assignee: Sony Corporation
    Inventors: Yuuki Yamagata, Ken Koseki, Masaru Kikuchi, Yoshiaki Inada, Junichi Inutsuka, Akari Tajima