Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Abstract: A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a.

Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Abstract: There is provided a nonvolatile semiconductor memory device and its writing method capable of controlling an increase in threshold voltage due to effects of adjacent memory cells and performing stable readout operations even if miniaturization of semiconductor memory devices proceeds further. The device comprises a memory cell array 411 having memory cells in a row and column directions, a row selection circuit 412, a column selection circuit 411, and a control circuit 405 for exercising writing control on a selected memory cell by an external command input. The control circuit performs a threshold voltage control for writing a memory cell selected as a writing target to a first predetermined threshold voltage when receiving a first external write command, and performs another threshold voltage control for writing the selected memory cell to a second predetermined threshold voltage different from the first threshold voltage when receiving a second external write command.

Abstract: A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.

Abstract: When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.

Abstract: A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states 1, 2, . . .

Abstract: A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.

Abstract: A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write or erase operation has been performed, to the memory element via the bit line, and a reset portion for grounding the bit line connected to the memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a current state of the write state machine, which is output from the write state machine, and outputting a status signal indicating a status of the program or erase operation with respect to the memory array, a status register for storing the status signal, and an output circuit for outputting the status signal stored in the status register. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements. Each memory element comprises a gate electrode, a channel region, first and second diffusion regions, and first and second memory function sections provided an opposite aides of the gate electrode and having a function of retaining charges. The device further comprises a row decoder for selecting a word line in accordance with a row address, and a write control circuit for applying a write pulse to a bit line, which is connected to one of the first and second diffusion regions of the memory element connected to the selected word line, in accordance with a column address. The write control circuit controls the application of the write pulse so that a quantity of charges retained in one of the first and second memory function sections corresponds to a value of multibit data.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising a plurality of memory elements, a section for performing an erase or program operation with respect to the memory array, a section for receiving a suspend command, and in response to the suspend command, suspending the erase or program operation, and a section for receiving a resume command, and in response to the resume command, resuming the suspended erase or program operation. Each of the plurality of memory elements comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundant

Abstract: A semiconductor memory device includes a controller programming a nonvolatile memory cell by applying a first pulse so that a charge amount smaller than a target charge amount is accumulated in the nonvolatile memory cell, a second pulse train so that a second charge amount smaller than the target charge amount and larger than the first charge amount is accumulated in the nonvolatile memory cell, and a third pulse train so that a third charge amount falling within an allowable error range of the target charge amount is accumulated. The semiconductor memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and memory functional units formed on both sides of the gate electrode.

Abstract: A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell.

Abstract: This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.

Abstract: A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the f