Abstract: A wiring substrate includes a core substrate including a glass substrate, a resin insulating layer including inorganic particles and resin, a conductor layer including a seed layer and an electrolytic plating layer such that the conductor layer includes signal wirings, and a via conductor formed in an opening formed in the resin insulating layer and including the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a through-hole conductor formed such that the core substrate has a through hole penetrating through the glass substrate and the through-hole conductor is formed in the through hole, the via conductor is electrically connected to the through-hole conductor formed in the core substrate, and the resin insulating layer is formed such that the surface upon which the conductor layer is formed includes the resin and an inner wall surface in the opening includes the resin and inorganic particles.

Abstract: A wiring substrate includes a first build-up part including first insulating layers and conductor layers, a second build-up part laminated to the first part and including second insulating layers and conductor layers, and via conductors including first via conductors in the first insulating layers and second via conductors in the second insulating layers. The first part is positioned closer to first surface side of the substrate than the second part. The first conductor layers include wirings having wiring width and inter-wiring distance that are smaller than wiring width and inter-wiring distance of wirings in the second conductor layers. The first insulating layers include resin and inorganic particles including first particles forming inner wall surfaces in through holes and second particles embedded in the first insulating layers having different shapes from the first particles. Each first conductor layers and via conductors includes a metal film layer and a plating film layer.

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Abstract: A wiring substrate includes a first build-up part including first insulating layers, first conductor layers formed on the first insulating layers, and first via conductors formed in the first insulating layers, and a second build-up part laminated to the first build-up part and including second insulating layers, second conductor layers formed on the second insulating layers, and second via conductors formed in the second insulating layers. A wiring width and an inter-wiring distance of wirings in the first conductor layers of the first build-up part are smaller than a wiring width and an inter-wiring distance of wirings in the second conductor layers of the second build-up part, and the first build-up part is formed such that the first insulating layers include insulating resin and inorganic particles and that the insulating resin in the first insulating layers forms the surfaces of the first insulating layers covered by the first conductor layers.

Abstract: A wiring substrate includes insulating layers including inorganic particles and resin, conductor layers formed on first surfaces of the insulating layers, respectively, and including the outermost conductor layer and a conductor layer, and via conductors formed in the insulating layers such that the via conductors are connecting the conductor layers formed on the first surfaces of the insulating layers. The conductor layers are formed such that the outermost conductor layer includes first conductor pads positioned to mount a first component and second conductor pads positioned to mount a second component and that the conductor layer includes first wiring patterns connecting the first conductor pads and the second conductor pads, and the insulating layers are formed such that the first surfaces of the insulating layers are formed of the resin and do not have exposed surfaces of the inorganic particles.

Abstract: A wiring substrate includes a first build-up part includes first insulating layers, first conductor layers and first via conductors, and a second build-up part laminated to the first build-up part and including second insulating layers, second conductor layers and second via conductors. The first conductor layers in the first build-up part and the second conductor layers in the second build-up part include wirings such that a wiring width and an inter-wiring distance of the wirings in the first conductor layers are smaller than a wiring width and an inter-wiring distance of the wirings in the second conductor layers, an aspect ratio of the wirings in the first conductor layers is in the range of 2.0 to 4.0, the wiring width of the wirings in the first conductor layers is 3 ?m or less, and the inter-wiring distance of the wirings in the first conductor layers is 3 ?m or less.

Abstract: A wiring substrate includes insulating layers, conductor layers formed on the insulating layers, and via conductors formed in the insulating layers such that the via conductors are connecting the conductor layers through the insulating layers. The conductor layers include a first conductor layer and the outermost conductor layer formed such that the outermost conductor layer includes first conductor pads positioned to mount a first component and second conductor pads positioned to mount a second component and that the first conductor layer includes wiring patterns including first wiring patterns connecting the first conductor pads and second conductor pads, and the first conductor layer in the conductor layers is formed such that the wiring patterns have the minimum wiring width of 3 ?m or less, the minimum inter-wiring distance of 3 ?m or less and an aspect ratio in the range of 2.0 to 4.0.

Abstract: A wiring substrate includes a core substrate; a first build-up part including first conductor layers, a second build-up part including second conductor layers, a third build-up part including third conductor layers and having the outermost surface of the wiring substrate, and a fourth build-up part including one or more fourth conductor layers and having the outermost surface of the wiring substrate. The minimum wiring width of wirings in the third conductor layers is smaller than that of wirings in the first, second and fourth conductor layers. The minimum inter-wiring distance of the wirings in the third conductor layers is smaller than that of the wirings in the first, second and fourth conductor layers. The wirings in the third conductor layers have the minimum wiring width of 3 ?m or less, the minimum inter-wiring distance of 3 ?m or less, and an aspect ratio in the range of 2.0 to 4.0.

Abstract: A wiring substrate includes an insulating layer, a first conductor layer formed on the insulating layer and including a first wiring and a second wiring formed adjacent to the first wiring, and a second conductor layer on the opposite side with respect to first conductor layer such that the insulating layer is covering the second conductor layer. The first conductor layer is formed such that each of the first wiring and the second wiring has an aspect ratio in the range of 2.0 to 4.0 and a wiring width of 5 ?m or less and that the first wiring and the second wiring are separated by the distance of 7 ?m or less, and the first conductor layer includes a seed layer formed on the insulating layer, and an electrolytic plating film formed on the seed layer.

Abstract: A method is provided for producing a three-dimensional object by stacking cured layers of a photocurable color ink composition containing a coloring material. The method includes applying the photocurable color ink composition onto an underlying member; and curing the photocurable color ink composition with light. The content of the coloring material in the photocurable color ink composition is in the range of 0.25% by mass to 2.1% by mass.

Abstract: When forming a 3D object by overlaying layers of an ink that solidifies to form 3D dots after being discharged, ink discharge data to discharge ink in each layer of the 3D object is produced employing formation data acquired for each layer of the 3D object. In order to produce this ink discharge data, halftone processing is performed on the formation data using a dithering method, and in the halftone processing for each of adjacent overlapping layers of the 3D object, a dither mask is applied in a different layout at equivalent positions in each layer of the 3D object formed by overlaying layers of the ink.

Abstract: Provided is a printing apparatus which prints by performing a halftoning process, by setting a block which is formed of a plurality of pixels as a unit, the apparatus including a first determination unit which determines whether or not a gradation value of each of the plurality of pixels satisfies a predetermined condition; a second determination unit which applies different conditions based on a determination result of the first determination unit, and determines whether or not to form a dot in at least one of the plurality of pixels; an error calculation unit which performs a calculation of a gradation error which occurs due to a determination result of the second determination unit, and a distribution of the calculated error to an unprocessed pixel by setting the block as a unit; and a dot forming unit which performs forming of dots using the determination result of the second determination unit.