Abstract: Various embodiments provide apparatuses, systems, and methods to determine a figure of merit (FOM) of a communication link (e.g., a serial communication link, also referred to herein as a channel) between a transmitter and a receiver. The FOM may be used to, for example, determine a health of the communication link during mission mode (normal operating mode), determine a modulation scheme to use for the communication link, determine a configuration to use for the receiver and/or transmitter, and/or another suitable use case. Other embodiments may be described and claimed.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90° from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.

Abstract: Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.

Abstract: A method for performing simulation includes determining whether a model is available for a channel. A model for the channel is generated using signal attenuation parameters provided by a user in response to determining that the model is unavailable. The model includes crosstalk characteristics from crosstalk parameters provided by the user.

Abstract: Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.

Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.

Abstract: A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.

Abstract: Systems and methods related to the configuration of data communication links between electrical devices are described. The methods described may consider power efficiency of the data communication link along with bit error rate, latency, data rate, and other specifications. Methods discussed may lead to changes in the data communication link protocol, use of error correction coding scheme, the power consumption and the selection of features employed by the data communication link. Electronic systems capable of implementing the discussed methods may be incorporated in the circuitry of the electrical devices. Methods discussed may change the configuration the data communication link features during the operation of the electrical devices and/or the data communication link.

Abstract: One embodiment of the present invention relates to a method for built-in self-measurement (BISM) of jitter components. A built-in self-measurement controller on the host integrated circuit (and, in some cases, a slave controller on a partner integrated circuit) may be used to control various switches to form various loopback circuits. A calibrated jittery data pattern is transmitted through each of the various loopback circuits. On-die instrumentation (ODI) circuitry may then be used to measure intrinsic jitter components for each loopback circuit via data representations such as eye-diagrams, or jitter histograms, or bit error ratio bathtub curves. The intrinsic jitter for link components (i.e. the jitter components such as deterministic jitter (DJ), random jitter (RJ), total jitter (TJ)) may then be determined based on the measured intrinsic jitters for the various loopback circuits. Other embodiments and features are also disclosed.

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system.

Abstract: One embodiment relates to a computer-implemented method that selects one of at least three procedures to determine equalization settings jointly for a transmitter and a receiver. A first process may be used if the end-of-channel signal-to-noise ratio (SNR) is greater than an SNR threshold and the equalization capability of the transmitter is greater than the equalization capability of the receiver. A second process may be used if the end-of-channel SNR is greater than the SNR threshold and the equalization capability of the transmitter is less than the equalization capability of the receiver. A third process may be used if the end-of-channel SNR is less than the SNR threshold. Other embodiments and features are also disclosed.

Abstract: An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.