Patents by Inventor Masashi Tsubuku

Masashi Tsubuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143281
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Application
    Filed: September 2, 2020
    Publication date: May 13, 2021
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
  • Patent number: 11004983
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Publication number: 20210119055
    Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 22, 2021
    Inventors: Tatsuya TODA, Masashi TSUBUKU
  • Publication number: 20210091226
    Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Michiaki SAKAMOTO, Takashi OKADA, Toshiki KANEKO, Tatsuya TODA
  • Patent number: 10957714
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Patent number: 10930720
    Abstract: One embodiment of the invention is characterized as follows. A display device comprising: a display area including a plurality of pixels, each of the pixels has a first TFT and a second TFT, the first TFT and the second TFT comprise an oxide semiconductor, the first TFT and the second TFT are covered by an interlayer insulating film, a first through hole is formed in the in the interlayer insulating film to connect a drain of the first TFT, wherein a distance d1 between a center of the first through hole and an edge of a channel of the first TFT is shorter than a distance d2 between a center of the first through hole and an edge of a channel of the second TFT, a channel length of the first TFT is shorter than a channel length of the second TFT.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Miyuki Ishikawa, Masashi Tsubuku
  • Patent number: 10923580
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10916663
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Patent number: 10892282
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: January 12, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Publication number: 20210005755
    Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 ?m to 100 ?m inclusive, preferably 3 ?m to 10 ?m inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or ?25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Hiromichi GODO
  • Publication number: 20210005771
    Abstract: The problem of the present disclosure is to provide a photo sensor circuit that uses oxide semiconductor transistors and the operation of which is stable. The photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takanori TSUNASHIMA, Marina MOCHIZUKI
  • Patent number: 10865470
    Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masashi Tsubuku
  • Publication number: 20200381472
    Abstract: According to one embodiment, an optical sensor device includes an insulating substrate, a first conductive layer and an optical sensor element disposed between the insulating substrate and the first conductive layer. The optical sensor element is electrically connected to the first conductive layer and covered by the first conductive layer. The optical sensor element includes a first semiconductor layer formed of an oxide semiconductor and controls an amount of charge flowing to the first conductive layer according to an amount of incident light to the first semiconductor layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 3, 2020
    Applicant: Japan Display Inc.
    Inventors: Takanori TSUNASHIMA, Masashi Tsubuku, Makoto Uchida
  • Patent number: 10854640
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yoshiaki Oikawa, Shunpei Yamazaki, Junichiro Sakata, Masashi Tsubuku, Kengo Akimoto, Miyuki Hosoba
  • Publication number: 20200335628
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
  • Patent number: 10777682
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Publication number: 20200286928
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Shunpei YAMAZAKI, Toshinari SASAKI, Junichiro SAKATA, Masashi TSUBUKU
  • Patent number: 10770597
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leadind to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Publication number: 20200212078
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
  • Publication number: 20200212223
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI