Patents by Inventor Masashi Tsubuku

Masashi Tsubuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387322
    Abstract: A semiconductor device including: an oxide semiconductor layer including a first surface and a second surface opposite to the first surface; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; and a pair of first electrode being in contact with the first surface of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer including a region in which composition ratio of nitrogen is 2 percent or more within a depth range of 2 nanometers from the first surface in a region vicinity of an edge of at least one of the first electrode of the pair of first electrode.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Applicant: Japan Display Inc.
    Inventors: Takaya TAMARU, Masashi TSUBUKU, Toshinari SASAKI, Hajime WATAKABE
  • Publication number: 20230369341
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Application
    Filed: April 20, 2023
    Publication date: November 16, 2023
    Inventors: Masahiro TAKAHASHI, Takuya HIROHASHI, Masashi TSUBUKU, Noritaka ISHIHARA, Masashi OOTA
  • Patent number: 11791415
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Publication number: 20230317834
    Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming a first metal oxide layer containing aluminum as a main component above a substrate; forming an oxide semiconductor layer above the first metal oxide layer; forming a gate insulating layer above the oxide semiconductor layer; forming a second metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the second metal oxide layer is formed above the gate insulating layer; removing the second metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 5, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20230317833
    Abstract: A method for manufacturing semiconductor device according to an embodiment includes; forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 5, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20230299209
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Application
    Filed: April 20, 2023
    Publication date: September 21, 2023
    Inventors: Hajime KIMURA, Kengo AKIMOTO, Masashi TSUBUKU, Toshinari SASAKI
  • Publication number: 20230292551
    Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).
    Type: Application
    Filed: March 1, 2023
    Publication date: September 14, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takeshi SAKAI, Kentaro MIURA, Hajime WATAKABE, Takaya TAMARU, Hiroshi TABATAKE, Yutaka UMEDA
  • Patent number: 11756966
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: September 12, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 11742432
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Publication number: 20230260785
    Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Masashi OOTA, Yoichi KUROSAWA, Noritaka ISHIHARA
  • Patent number: 11695019
    Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: July 4, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yoshiaki Oikawa, Shunpei Yamazaki, Junichiro Sakata, Masashi Tsubuku, Kengo Akimoto, Miyuki Hosoba
  • Publication number: 20230209850
    Abstract: According to one embodiment, a display device includes an anode, an organic EL element layer including a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer, and a cathode, wherein ?E2_LUMO is defined as a potential barrier between the electron transport layer and the hole blocking layer, and the light-emitting layer, ?E2_HOMO is defined as a potential barrier between the hole transport layer and the electron blocking layer, and the light-emitting layer, and each of ?E2_LUMO and ?E2_HOMO is 0.1 eV or higher and 0.5 eV or less.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 29, 2023
    Applicant: Japan Display Inc.
    Inventors: Nobuto MANAGAKI, Takuya NAKAGAWA, Ryosuke MURATA, Masakazu GUNJI, Takahiro USHIKUBO, Masashi TSUBUKU
  • Publication number: 20230187558
    Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 15, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Michiaki SAKAMOTO, Takashi OKADA, Toshiki KANEKO, Tatsuya TODA
  • Publication number: 20230169922
    Abstract: A display device including a substrate, a light-emitting element, a first transistor, and a second transistor, the first transistor including the first gate electrode on the substrate; a first insulating film on the first gate electrode, a first oxide semiconductor on the first insulating film, and having an area overlapping the first gate electrode, a second insulating film on the first oxide semiconductor, and a first conductive layer on the second insulating film, the second transistor including the first insulating film on the substrate, a second oxide semiconductor on the first insulating film, a second insulating film on the first oxide semiconductor and the second oxide semiconductor, and having a thickness smaller than a thickness of the first insulating film, a second gate electrode on the second insulating film, and having an area overlapping the second oxide semiconductor.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 1, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Kentaro MIURA, Masashi TSUBUKU
  • Patent number: 11652174
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: May 16, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
  • Patent number: 11652110
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 16, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Publication number: 20230137257
    Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takanori TSUNASHIMA, Marina MOCHIZUKI
  • Publication number: 20230138390
    Abstract: According to one embodiment, an optical sensor device includes an insulating substrate, a first conductive layer and an optical sensor element disposed between the insulating substrate and the first conductive layer. The optical sensor element is electrically connected to the first conductive layer and covered by the first conductive layer. The optical sensor element includes a first semiconductor layer formed of an oxide semiconductor and controls an amount of charge flowing to the first conductive layer according to an amount of incident light to the first semiconductor layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Applicant: Japan Display Inc.
    Inventors: Takanori TSUNASHIMA, Masashi TSUBUKU, Makoto UCHIDA
  • Patent number: 11637015
    Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: April 25, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara
  • Publication number: 20230108412
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 6, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU