Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.

Abstract: In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.

Abstract: Source and drain diffusion layers by an extremely shallower box shaped highly doped impurity distribution that was not obtainable so far by the existent solid phase growing is attained by liquid phase growing with no effects on the gate electrode thereby attaining low consumption power and operation at large current and higher speed in a micro-refined semiconductor device. Contact with inter-connection layer over the entire region of the source and drain diffusion layers is enabled overstriding the gate electrode and without short circuit with the gate electrode by utilizing that the etching selectivity of an insulation film comprising Al as a main constituent atom is extremely higher with respect to an Si oxide film.

Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.

Abstract: A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other, in which a multi-layered SOI substrate having an amorphous or polycrystal semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate.

Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.

Abstract: Source-drain diffusion regions of a shallow junction and a stacked metal silicide film structure of a low resistance in a miniaturized MIS transistor are to be attained while ensuring high reliability. The concentration of an impurity (As, P, In, Sb) in surface areas of source-drain diffusion regions (6, 7) is set to a value of not smaller than 5×1021/cm3. Alternatively, an alloy film of germanium and silicon containing not less than 20% of germanium, or germanium film, is formed on surface areas of the source-drain diffusion regions (6, 7).

Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: A semiconductor integrated circuit has a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate electrode with the MOS transistor, whereby the body potential of the MOS transistor is controlled by gate and drain potentials. Accumulated body charge in a non-conducting state in the semiconductor integrated circuit is extracted by a resistor formed between the body node and a source, whereby various phenomena caused by the floating body effect are eliminated. The threshold voltage of the MOS transistor can be made variable so as to follow a change in an input signal.

Abstract: Disclosed is a method of manufacturing a semiconductor device capable of improving the reliability of the semiconductor device, which has a field effect transistor having a source-drain structure with a shallow junction. In the process for realizing the reduction of the resistance in a diffusion layer for a source and drain with a shallow junction, in which a part of an amorphous layer formed by the ion implantation for forming a diffusion layer for a source and drain is selectively melted and recrystallized by the use of laser irradiation, in order to prevent the occurrence of defects such as short circuit at a portion where a region to be melted and a gate electrode are overlapped with each other, ion implantation is performed after the formation of a first gate sidewall insulator on a sidewall of the gate electrode so as to obtain a structure in which the amorphous layer is not overlapped with the gate electrode.

Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

Abstract: A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other,

Abstract: A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.