Patents by Inventor Masataka Mizukoshi

Masataka Mizukoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Publication number: 20150094664
    Abstract: A drug delivery device includes a cylindrical casing which has two openings on opposite sides, a lid which has an air inflow hole and is joined at one end of the cylindrical casing so as to close one of the openings. An internal space, in which an inflating agent and a drug are sealed while being separated from each other, is formed by at least the cylindrical casing and the lid, the internal space communicates with the air inflow hole and a delivery hole through which the drug is delivered, the inflating agent is formed of a material which is mainly composed of iron, iron oxide is produced by at least oxygen in the inflow air, which causes the inflating agent to be inflated, and as the inflating agent is inflated, the drug is delivered through the delivery hole.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Applicant: SYNDEO LLC
    Inventor: Masataka MIZUKOSHI
  • Patent number: 8962470
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8915418
    Abstract: The present invention ensures a good bonding state between the electrode terminals of electronic components and the electrodes of a substrate, and achieves an increase in productivity and a downsizing of the substrate. The present invention includes: an applying step of applying a metal fine powder paste on each of multiple electrodes that are provided on a substrate; a component placing step of placing multiple electronic components with different heights, on the multiple electrodes, respectively; an organic film placing step of placing an organic film on the multiple electronic components; an organic film compressing step of applying a first pressure to the electronic component side with a pressing member and equalizing the height of the organic film; and a bonding step of applying a second pressure to the electronic component side with a compressing member on heating for a predetermined time and sintering the metal fine powder paste.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 23, 2014
    Assignees: Tadatomo Suga, Masataka Mizukoshi, Alpha Design Co., Ltd.
    Inventors: Toshiyuki Shiratori, Toru Kawasaki, Tadatomo Suga, Masataka Mizukoshi
  • Patent number: 8875977
    Abstract: An element pressing apparatus includes: a base casing having first and second bases couplable to or separable from each other to form an arrangement space where a board and a plurality of electronic components having different heights are arranged while the first and second bases are coupled to each other; oil encapsulated in the arrangement space; an oil seal member deformed depending on a pressure of the oil; and a hydraulic pressure change portion that changes the pressure of the oil, wherein the pressure of the oil changes by the hydraulic pressure change portion to press the oil seal member to a plurality of electronic components and press the electrode terminals against the electrodes when the board and a plurality of electronic components are arranged in the arrangement space by positioning and placing each of the electrode terminals on each of the electrodes.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: November 4, 2014
    Assignee: Alpha Design Co., Ltd.
    Inventors: Toshiyuki Shiratori, Toru Kawasaki, Tadatomo Suga, Masataka Mizukoshi
  • Publication number: 20140263581
    Abstract: The present invention ensures a good bonding state between the electrode terminals of electronic components and the electrodes of a substrate, and achieves an increase in productivity and a downsizing of the substrate. The present invention includes: an applying step of applying a metal fine powder paste on each of multiple electrodes that are provided on a substrate; a component placing step of placing multiple electronic components with different heights, on the multiple electrodes, respectively; an organic film placing step of placing an organic film on the multiple electronic components; an organic film compressing step of applying a first pressure to the electronic component side with a pressing member and equalizing the height of the organic film; and a bonding step of applying a second pressure to the electronic component side with a compressing member on heating for a predetermined time and sintering the metal fine powder paste.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: ALPHA DESIGN CO., LTD.
    Inventors: Toshiyuki SHIRATORI, Toru KAWASAKI, Tadatomo SUGA, Masataka MIZUKOSHI
  • Publication number: 20140263575
    Abstract: An element pressing apparatus includes: a base casing having first and second bases couplable to or separable from each other to form an arrangement space where a board and a plurality of electronic components having different heights are arranged while the first and second bases are coupled to each other; oil encapsulated in the arrangement space; an oil seal member deformed depending on a pressure of the oil; and a hydraulic pressure change portion that changes the pressure of the oil, wherein the pressure of the oil changes by the hydraulic pressure change portion to press the oil seal member to a plurality of electronic components and press the electrode terminals against the electrodes when the board and a plurality of electronic components are arranged in the arrangement space by positioning and placing each of the electrode terminals on each of the electrodes.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: ALPHA DESIGN CO., LTD.
    Inventors: Toshiyuki SHIRATORI, Toru KAWASAKI, Tadatomo SUGA, Masataka MIZUKOSHI
  • Patent number: 8735274
    Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Taisuke Iwai
  • Patent number: 8704106
    Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki
  • Patent number: 8479386
    Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 8409931
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Taiji Sakai, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Patent number: 8293577
    Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Masataka Mizukoshi
  • Publication number: 20120244665
    Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Nobuhiro Imaizumi, Masataka Mizukoshi
  • Patent number: 8216934
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Patent number: 8058110
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 15, 2011
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Publication number: 20110220397
    Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki
  • Publication number: 20110168564
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Application
    Filed: March 9, 2011
    Publication date: July 14, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Patent number: 7935573
    Abstract: The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the second substrate 12, enclosing the predetermined region of the first substrate 10, and an adhesion layer 42 formed on the side surfaces of the sealing parts 26, 40. The adhesion layer is formed on the side surfaces of the first sealing structure 26 on the side of the first substrate 10 and the second sealing structure 40 on the side of the second substrate 12, whereby when the first sealing structure 26 and the second sealing structure 40 are bonded to each other, the adhesion between the first sealing structure 26 and the second sealing structure 40 can be sufficiently ensured.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventor: Masataka Mizukoshi
  • Publication number: 20110092065
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Eiji YOSHIDA, Takao OHNO, Yoshito AKUTAGAWA, Koji SAWAHATA, Masataka MIZUKOSHI, Takao NISHIMURA, Akira TAKASHIMA, Mitsuhisa WATANABE
  • Patent number: 7927998
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki