Patents by Inventor Masataka Mizukoshi

Masataka Mizukoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060170089
    Abstract: The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the second substrate 12, enclosing the predetermined region of the first substrate 10, and an adhesion layer 42 formed on the side surfaces of the sealing parts 26, 40. The adhesion layer is formed on the side surfaces of the first sealing structure 26 on the side of the first substrate 10 and the second sealing structure 40 on the side of the second substrate 12, whereby when the first sealing structure 26 and the second sealing structure 40 are bonded to each other, the adhesion between the first sealing structure 26 and the second sealing structure 40 can be sufficiently ensured.
    Type: Application
    Filed: June 8, 2005
    Publication date: August 3, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Masataka Mizukoshi
  • Patent number: 7049229
    Abstract: An insulating film having openings larger than viaholes, formed as being aligned with the viaholes, is coated on the back surface of a silicon semiconductor substrate so that the viaholes fall within the openings, a conductive film is then formed so as to fill the viaholes and the openings by plating, vacuum evaporation or a technique using a metal paste, and the conductive film is then cut using a bite to thereby form through electrodes.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: May 23, 2006
    Assignee: Fujitsu Limited
    Inventors: Koji Omote, Masataka Mizukoshi
  • Publication number: 20060084251
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 so that the ten-point height of irregularities of the surface of the resin layer 10 is 0.5-5 ?m; the step of forming a seed layer 36 on the resin layer 10; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Application
    Filed: February 28, 2005
    Publication date: April 20, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Takeshi Shioga, Masataka Mizukoshi, Kazuaki Kurihara, John Baniecki
  • Publication number: 20060084253
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Application
    Filed: October 17, 2005
    Publication date: April 20, 2006
    Applicant: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John Baniecki
  • Publication number: 20060027936
    Abstract: Electrodes and an insulating film are both formed of materials which have characteristics that they are solid and do not exhibit adhesiveness at a room temperature, exhibit adhesiveness at and above a first temperature higher than this, and are cured at and above a second temperature higher than this. Planarication processing is carried out by performing cutting with a hard cutting tool made of diamond and the like so that surfaces film the electrodes and a surface of the insulating film become continuously planar.
    Type: Application
    Filed: December 22, 2004
    Publication date: February 9, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Publication number: 20060030071
    Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 9, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
  • Patent number: 6979644
    Abstract: A method of manufacturing an electronic circuit component, including the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: December 27, 2005
    Assignee: Fujitsu Limited
    Inventors: Koji Omote, Masataka Mizukoshi, Osamu Taniguchi
  • Publication number: 20050227474
    Abstract: The present invention is aimed at providing a method of connecting base materials capable of forming metal terminals having a uniform height and smooth surface with a low cost, and of realizing a low-damage mounting, in which a work is planarized while keeping the temperature of the insulating film, possibly elevated due to frictional heat generated during cutting using a cutting tool, lower than 80° C., and keeping the temperature range lower than 80° C. throughout the entire period of the cutting, the electrodes and electrodes are opposed and brought into contact at a temperature of 80° C. or above but lower than the curing temperature of the insulating film, the insulating film is liquefied and a space between the electrodes and electrodes is filled with an insulating resin composing the insulating film, and the insulating resin is cured at the curing temperature or above.
    Type: Application
    Filed: December 23, 2004
    Publication date: October 13, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Taiji Sakai
  • Patent number: 6943447
    Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: September 13, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi
  • Publication number: 20050170640
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Application
    Filed: April 1, 2005
    Publication date: August 4, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
  • Publication number: 20050167812
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 4, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20050161814
    Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: March 21, 2005
    Publication date: July 28, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Publication number: 20050109533
    Abstract: A manufacturing method of a circuit board includes the steps of: forming projecting electrodes on a substrate; forming a photosensitive resin film on the substrate so as to cover the projecting electrodes; exposing a substantially entire surface of the photosensitive film; and melting the surface of the photosensitive film so as to expose the projecting electrodes.
    Type: Application
    Filed: December 28, 2004
    Publication date: May 26, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Mamoru Kurashina, Yoshikatsu Ishizuki, Nawalage Cooray, Masataka Mizukoshi
  • Patent number: 6896998
    Abstract: A pattern forming method comprising the steps of: detecting a position of a base pattern formed on a substrate; forming a photosensitive resin film on the substrate; correcting a pattern data of a pattern to be formed on the substrate, based on a positional information of the base pattern to thereby compute a corrected pattern data; displaying a mask pattern on a liquid crystal panel, based on the corrected pattern data; and exposing the photosensitive resin film with the liquid crystal panel as a mask and developing the same to thereby pattern the photosensitive resin film. Even when a base pattern has rotations, shrinkages, distortions, etc., a prescribed upper layer pattern can be formed in alignment with the lower layer pattern.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 24, 2005
    Assignee: Fujitsu Limited
    Inventor: Masataka Mizukoshi
  • Patent number: 6893681
    Abstract: A process to manufacture a surface-conductive resin in a short time at a low cost without damaging the main chain of a polymer is provided. The process for manufacturing surface-conductive resin comprises partially substituting a reactive group in at least one of a resin precursor and a semi-cured resin having at least one reactive group partially substitutable under alkaline condition by an alkali metal ion solution, exchanging the substituted alkali metal ion with the ion of a conductive material in the ionic solution, reducing the ion of the conductive material to deposit the conductive layer, then curing the resin, to get surface-conductive polymer/resin.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Nawalage Florence Cooray, Kanae Nakagawa, Masataka Mizukoshi
  • Publication number: 20050026335
    Abstract: An insulating film having openings larger than viaholes, formed as being aligned with the viaholes, is coated on the back surface of a silicon semiconductor substrate so that the viaholes fall within the openings, a conductive film is then formed so as to fill the viaholes and the openings by plating, vacuum evaporation or a technique using a metal paste, and the conductive film is then cut using a bite to thereby form through electrodes.
    Type: Application
    Filed: May 25, 2004
    Publication date: February 3, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Koji Omote, Masataka Mizukoshi
  • Patent number: 6806118
    Abstract: An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: October 19, 2004
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Masataka Mizukoshi, Yasuo Yamagishi
  • Patent number: 6773947
    Abstract: According to the present invention, of the resist film applied to the entire surface of the silicon substrate, the part on the electrode pattern is removed and an opening shaped like a dish in which the diameter of the upper part is larger than that of the lower part is formed, wherein the diameter of the lower part is smaller than the outer diameter of the electrode pattern. The electrode pattern exposed at the bottom of the opening is removed by the etching process. Next, the silicon substrate is tilted and a laser beam is irradiated toward the silicon substrate exposed at the bottom of the opening with water running over the surface of the resist film in air, and a hole is formed.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventor: Masataka Mizukoshi
  • Patent number: 6732911
    Abstract: There is provided a chamber open to the outside through openings through which a solder-adhered object is passed and the chamber having a heating/melting area, a carrying mechanism for carrying the solder-adhered object into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to create a lower pressure area in the heating/melting area as compared to the pressure of outside the chamber, heating means for heating directly or indirectly the solder-adhered object in the heating/melting area, and an air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 11, 2004
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Hiroyuki Matsui, Eiji Yoshida, Takao Ohno, Koki Otake, Akiyo Mizutani, Motoshu Miyajima, Masataka Mizukoshi, Eiji Watanabe
  • Publication number: 20040009666
    Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material. A printed circuit board comprising a signal line conductor formed on a first insulating layer which selectively covers a first ground layer spreading on a substrate, shield walls extending across gaps on both sides of the signal line conductor, and conductively connected to the first ground layer, and a second ground layer conductively connected to the shield walls, stretching across gaps above the signal line conductor, and in which a plurality of openings having lengths and distances of equal to or less than one quarter of a frequency handled by the signal line conductor are formed, is also disclosed.
    Type: Application
    Filed: January 9, 2003
    Publication date: January 15, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi