Patents by Inventor Masatake Hangai

Masatake Hangai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013854
    Abstract: CRLH lines including left-handed shunt inductors and left-handed series capacitors are provided on gate side transmission lines of a plurality of FETs.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Jun KAMIOKA, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20210013849
    Abstract: A stub whose end is connected to an end of a transmission line, and a coupled line disposed in parallel with each of the transmission line and the stub, and electromagnetically coupled to each of the transmission line and the stub are included, and the stub and the coupled line operate as a first resonator for resonating with an odd order harmonic included in the amplified signal, and the transmission line, the stub, and the coupled line operate as a second resonator for resonating with an even order harmonic included in the amplified signal.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takumi SUGITANI, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20210005535
    Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Shintaro SHINJO, Koji YAMANAKA
  • Publication number: 20200403401
    Abstract: A switch element is arranged between an input terminal and an output terminal. A signal from the input terminal is distributed by a capacitative element and supplied to the cathode side of a diode. An inductor is connected to the cathode side of the diode, and a smoothing circuit including a capacitative element and a resistor is connected to the anode side. The switch element has a control terminal connected to the anode of the diode, and turns off a path between the input terminal and the output terminal when a voltage is applied to the control terminal.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuma TORII, Masatake HANGAI, Koji YAMANAKA, Kazuhiro NISHIDA
  • Publication number: 20200389199
    Abstract: A first inductor is connected to an input terminal through a capacitive element. To the first inductor, an anti-parallel diode pair including a first diode and a second diode, and a second inductor are connected. The first inductor and the anti-parallel diode pair are coupled to each other by an electromagnetic field, thereby forming a coupling capacitance.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuma TORII, Masatake HANGAI, Koji YAMANAKA, Kazuhiro NISHIDA
  • Patent number: 10797141
    Abstract: A semiconductor device includes: an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 6, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10777550
    Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 15, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10763797
    Abstract: A high-frequency power amplifier is configured to include plural island patterns (28) in which ends thereof are arranged in the vicinity of a transmission line (23) and other ends thereof are arranged in the vicinity of an end line (24a) in a transmission line (24), a wire (30) for connecting an end of an island pattern (28) and the transmission line (23), and a wire (31) for connecting another end of the island pattern (28) and the end line (24a) of the second transmission line (24), so that a mismatch of the impedance component having a resistance component and a reactance component can be compensated for by changing the number of first connecting members and the number of second connecting members, the first and second connecting members configured to connect an island pattern (28) to the transmission lines (23) and (24).
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 1, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaaki Yoshioka, Masatake Hangai, Koji Yamanaka
  • Patent number: 10741700
    Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Publication number: 20200235215
    Abstract: A semiconductor device includes; an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.
    Type: Application
    Filed: July 25, 2016
    Publication date: July 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20200152803
    Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.
    Type: Application
    Filed: May 18, 2017
    Publication date: May 14, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Patent number: 10439262
    Abstract: There are provided: a first capacitor connected between first and second input/output terminals; a second capacitor connected between the first input/output terminal and a third input/output terminal; a first inductor having one end connected to the first input/output terminal; a second inductor having one end connected to the second input/output terminal and another end connected to another end of the first inductor; a third inductor having one end connected to the first input/output terminal; a fourth inductor having one end connected to the third input/output terminal and another end connected to another end of the third inductor; a first transistor having a drain terminal connected to said another ends of the first and second inductors and a source terminal that is grounded; and a second transistor having a drain terminal connected to said another ends of the third and fourth inductors and a source terminal that is grounded.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 8, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ryota Komaru, Masatake Hangai, Koji Yamanaka
  • Publication number: 20190296010
    Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).
    Type: Application
    Filed: December 16, 2016
    Publication date: September 26, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro YAMAGUCHI, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20190296701
    Abstract: A wire (14) having a first end connected to a line (2) and a second end connected to a second end of a resistor (9) and having an inductive component La resonating with a parasitic capacitance Ca of the resistor (9), or a wire (16) having a first end connected to a line (3) and a second end connected to a second end of a resistor (12) and having an inductive component Lb resonating with a parasitic capacitance Cb of the resistor (12) are provided. Consequently, gain flatness in an operating frequency band can be improved.
    Type: Application
    Filed: December 19, 2016
    Publication date: September 26, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaaki YOSHIOKA, Masatake HANGAI, Koji YAMANAKA
  • Patent number: 10361483
    Abstract: The antenna device includes: an element part 100 having an excitation element 1, a first passive element 11 having first and second conductive parts 11a and 11b, a second passive element 21 having third and fourth conductive parts 21a and 21b, a first switch 12 controlling conduction between the first and second conductive parts, and a second switch 22 controlling conduction between the third and fourth conductive parts; and a controller 200 outputting an electric signal for controlling conduction of the first and second switches. The controller outputs identical DC signal to the first and second switches, and one of the first and second switches is brought into conduction while the other one is brought out of conduction.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Maruyama, Satoshi Yamaguchi, Masataka Otsuka, Masatake Hangai, Naoyuki Yamamoto
  • Publication number: 20190131937
    Abstract: A high-frequency power amplifier is configured to include plural island patterns (28) in which ends thereof are arranged in the vicinity of a transmission line (23) and other ends thereof are arranged in the vicinity of an end line (24a) in a transmission line (24), a wire (30) for connecting an end of an island pattern (28) and the transmission line (23), and a wire (31) for connecting another end of the island pattern (28) and the end line (24a) of the second transmission line (24), so that a mismatch of the impedance component having a resistance component and a reactance component can be compensated for by changing the number of first connecting members and the number of second connecting members, the first and second connecting members configured to connect an island pattern (28) to the transmission lines (23) and (24).
    Type: Application
    Filed: May 19, 2016
    Publication date: May 2, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takaaki YOSHIOKA, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20180301778
    Abstract: There are provided: a first capacitor connected between first and second input/output terminals; a second capacitor connected between the first input/output terminal and a third input/output terminal; a first inductor having one end connected to the first input/output terminal; a second inductor having one end connected to the second input/output terminal and another end connected to another end of the first inductor; a third inductor having one end connected to the first input/output terminal; a fourth inductor having one end connected to the third input/output terminal and another end connected to another end of the third inductor; a first transistor having a drain terminal connected to said another ends of the first and second inductors and a source terminal that is grounded; and a second transistor having a drain terminal connected to said another ends of the third and fourth inductors and a source terminal that is grounded.
    Type: Application
    Filed: December 9, 2015
    Publication date: October 18, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryota KOMARU, Masatake HANGAI, Koji YAMANAKA
  • Publication number: 20170207529
    Abstract: The antenna device includes: an element part 100 having an excitation element 1, a first passive element 11 having first and second conductive parts 11a and 11b, a second passive element 21 having third and fourth conductive parts 21a and 21b, a first switch 12 controlling conduction between the first and second conductive parts, and a second switch 22 controlling conduction between the third and fourth conductive parts; and a controller 200 outputting an electric signal for controlling conduction of the first and second switches. The controller outputs identical DC signal to the first and second switches, and one of the first and second switches is brought into conduction while the other one is brought out of conduction.
    Type: Application
    Filed: August 3, 2015
    Publication date: July 20, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi MARUYAMA, Satoshi YAMAGUCHI, Masataka OTSUKA, Masatake HANGAI, Naoyuki YAMAMOTO
  • Patent number: 8618878
    Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: December 31, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masatake Hangai, Kazutomi Mori, Kenichi Tajima, Yukihiro Tahara, Morishige Hieda
  • Publication number: 20130175544
    Abstract: It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (3) through which electrons travel; a barrier layer (4) which is provided on the GaN channel layer in order to form two-dimensional electron gas in the GaN channel layer and which contains at least any one of In, Al, and Ga and contains N; a gate electrode (8), a source electrode (6), and a drain electrode (7); and a plate (20) formed of a material having polarization, which is provided between the gate electrode (8) and the drain electrode (7), the plate being held in contact with a part of the barrier layer (4).
    Type: Application
    Filed: November 10, 2010
    Publication date: July 11, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka, Kazuhisa Yamauchi, Masatake Hangai, Masatoshi Nakayama