Abstract: A semiconductor device includes; an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.

Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.

Abstract: There are provided: a first capacitor connected between first and second input/output terminals; a second capacitor connected between the first input/output terminal and a third input/output terminal; a first inductor having one end connected to the first input/output terminal; a second inductor having one end connected to the second input/output terminal and another end connected to another end of the first inductor; a third inductor having one end connected to the first input/output terminal; a fourth inductor having one end connected to the third input/output terminal and another end connected to another end of the third inductor; a first transistor having a drain terminal connected to said another ends of the first and second inductors and a source terminal that is grounded; and a second transistor having a drain terminal connected to said another ends of the third and fourth inductors and a source terminal that is grounded.

Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).

Abstract: A wire (14) having a first end connected to a line (2) and a second end connected to a second end of a resistor (9) and having an inductive component La resonating with a parasitic capacitance Ca of the resistor (9), or a wire (16) having a first end connected to a line (3) and a second end connected to a second end of a resistor (12) and having an inductive component Lb resonating with a parasitic capacitance Cb of the resistor (12) are provided. Consequently, gain flatness in an operating frequency band can be improved.

Abstract: The antenna device includes: an element part 100 having an excitation element 1, a first passive element 11 having first and second conductive parts 11a and 11b, a second passive element 21 having third and fourth conductive parts 21a and 21b, a first switch 12 controlling conduction between the first and second conductive parts, and a second switch 22 controlling conduction between the third and fourth conductive parts; and a controller 200 outputting an electric signal for controlling conduction of the first and second switches. The controller outputs identical DC signal to the first and second switches, and one of the first and second switches is brought into conduction while the other one is brought out of conduction.

Abstract: A high-frequency power amplifier is configured to include plural island patterns (28) in which ends thereof are arranged in the vicinity of a transmission line (23) and other ends thereof are arranged in the vicinity of an end line (24a) in a transmission line (24), a wire (30) for connecting an end of an island pattern (28) and the transmission line (23), and a wire (31) for connecting another end of the island pattern (28) and the end line (24a) of the second transmission line (24), so that a mismatch of the impedance component having a resistance component and a reactance component can be compensated for by changing the number of first connecting members and the number of second connecting members, the first and second connecting members configured to connect an island pattern (28) to the transmission lines (23) and (24).

Abstract: There are provided: a first capacitor connected between first and second input/output terminals; a second capacitor connected between the first input/output terminal and a third input/output terminal; a first inductor having one end connected to the first input/output terminal; a second inductor having one end connected to the second input/output terminal and another end connected to another end of the first inductor; a third inductor having one end connected to the first input/output terminal; a fourth inductor having one end connected to the third input/output terminal and another end connected to another end of the third inductor; a first transistor having a drain terminal connected to said another ends of the first and second inductors and a source terminal that is grounded; and a second transistor having a drain terminal connected to said another ends of the third and fourth inductors and a source terminal that is grounded.

Abstract: The antenna device includes: an element part 100 having an excitation element 1, a first passive element 11 having first and second conductive parts 11a and 11b, a second passive element 21 having third and fourth conductive parts 21a and 21b, a first switch 12 controlling conduction between the first and second conductive parts, and a second switch 22 controlling conduction between the third and fourth conductive parts; and a controller 200 outputting an electric signal for controlling conduction of the first and second switches. The controller outputs identical DC signal to the first and second switches, and one of the first and second switches is brought into conduction while the other one is brought out of conduction.

Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.

Abstract: It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (3) through which electrons travel; a barrier layer (4) which is provided on the GaN channel layer in order to form two-dimensional electron gas in the GaN channel layer and which contains at least any one of In, Al, and Ga and contains N; a gate electrode (8), a source electrode (6), and a drain electrode (7); and a plate (20) formed of a material having polarization, which is provided between the gate electrode (8) and the drain electrode (7), the plate being held in contact with a part of the barrier layer (4).

Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.

Abstract: A switch circuit includes: a first input and output terminal; a first inductor connected with the first input and output terminal; a capacitor connected with the first inductor; a second input and output terminal connected with the capacitor; a first MEMS switch connected with one end of the capacitor; a second MEMS switch connected with the other end of the capacitor; and a second inductor connected between the first MEMS switch and the second MEMS switch, and satisfies a relationship of f=1/(2??CL1)=1/(2??CL2), where L1 is an inductance of the first inductor, L2 is an inductance of the second inductor, C is a capacitance of the capacitor, and f is a use frequency.

Abstract: A single pole single throw switch for controlling propagation of a high frequency signal between an input terminal (11a) and an output terminal (11b). First FET switches (14a, 14b) in which drains and sources of FETs (12a, 12b) are connected in parallel with inductors (13a, 13b) are connected in parallel. Each FET (12a, 12b) is switched between on state and off state by a voltage being applied to the gate thereof. At the frequency of the high frequency signal, each inductor (13a, 13b) connected with off capacitor of each FET (12a, 12b) resonates in parallel.

Abstract: The present invention provides a high-frequency switch including: a first switching element connected between a first input/output terminal and a second input/output terminal; a second switching element connected between the second input/output terminal and the first switching element; a high-frequency line provided between the first input/output terminal, the first switching element, and a third input/output terminal; and a third switching element connected between the third input/output terminal, the high-frequency line, and a ground. By connecting the first switching element, the second switching element, the high-frequency line, and the third switching element, because there exists no FET through which a large current flows when a state between the first input/output terminal and the third input/output terminal is set to a transmission state which requires high power handling capability, there is no need to use an FET having a large gate width, which is effective in reducing a loss of the switch.

Abstract: A phase-shifting circuit includes: a first parallel circuit which is connected across input and output terminals of a high frequency signal, composed of a first inductor and a first switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the first switching element is in the OFF state; a series circuit composed of a second inductor and a third inductor and connected in parallel with the first parallel circuit; a capacitor having its first terminal connected to a point of connection of the second and third inductors; and a second parallel circuit which is connected across a second terminal of the capacitor and a ground, composed of a fourth inductor and a second switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the second switching element is in the OFF state.

Abstract: Provided is a small-size phase shift circuit having a broad band characteristic. The phase shift circuit includes: a first switching element for switching between a through path and a capacitance capacity; a second switching element for switching the capacitance capacity for the through path and the ground; and a first and a second inductor having inductance. One end of the first switching element is connected to one end of the second switching element by the first inductor while the other ends of the first and the second switching element are connected to each other by the second inductor. One end of the first switching element is connected to a high-frequency signal input terminal while the other end of the first switching element is connected to a high-frequency signal output terminal. Thus, it is possible to constitute a phase device satisfying a predetermined condition.

Abstract: A switch circuit including: a plurality of MEMS switches connected in parallel or in series, which have different drive voltages; and a single voltage supply for driving the plurality of MEMS switches by the plurality of drive voltages, is used for a microwave circuit or an antenna circuit, to vary a configuration of the microwave circuit or the antenna circuit based on the drive voltage value. That is, the configuration of the microwave circuit or the antenna circuit can be varied based on the drive voltage value by using the switch circuit including the MEMS switches having the different drive voltages for the microwave circuit or the antenna circuit.

Abstract: A single pole single throw switch for controlling propagation of a high frequency signal between an input terminal (11a) and an output terminal (11b). First FET switches (14a, 14b) in which drains and sources of FETs (12a, 12b) are connected in parallel with inductors (13a, 13b) are connected in parallel. Each FET (12a, 12b) is switched between on state and off state by a voltage being applied to the gate thereof. At the frequency of the high frequency signal, each inductor (13a, 13b) connected with off capacitor of each FET (12a, 12b) resonates in parallel.

Abstract: A switch circuit includes: a first input and output terminal; a first inductor connected with the first input and output terminal; a capacitor connected with the first inductor; a second input and output terminal connected with the capacitor; a first MEMS switch connected with one end of the capacitor; a second MEMS switch connected with the other end of the capacitor; and a second inductor connected between the first MEMS switch and the second MEMS switch, and satisfies a relationship of f=1/(2??CL1)=1/(2??CL2), where L1 is an inductance of the first inductor, L2 is an inductance of the second inductor, C is a capacitance of the capacitor, and f is a use frequency.