Patents by Inventor Masato Kijima

Masato Kijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130130113
    Abstract: The invention relates to positive electrode for lithium secondary battery which comprises an active material and a conductive material, wherein the active material comprises a lithium-transition metal compound which has a function of being capable of insertion and desorption of lithium ion, the lithium-transition metal compound gives a surface-enhanced Raman spectrum which has a peak at 800-1,000 cm?1, and the conductive material comprises carbon black which has a nitrogen adsorption specific surface area (N2SA) of 70-300 m2/g and an average particle diameter of 10-35 nm, and a lithium secondary battery which employs the same.
    Type: Application
    Filed: January 16, 2013
    Publication date: May 23, 2013
    Inventors: Shoji TAKANO, Kenji Shizuka, Jungmin Kim, Tomohiro Kusano, Masato Kijima
  • Publication number: 20130011726
    Abstract: The invention relates to a lithium-transition metal compound powder for a positive-electrode material for lithium secondary battery which comprises secondary particles configured of primary particles having two or more compositions and a lithium-transition metal compound having a function of being capable of insertion and release of lithium ions, wherein the powder gives a pore distribution curve having a peak at a pore radium 80 nm or greater but less than 800 nm, and the secondary particles include primary particles of a compound represented by a structural formula including at least one element selected from As, Ge, P, Pb, Sb, Si and Sn, wherein the primary particles of the compound are present at least in an inner part of the secondary particles.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 10, 2013
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Shoji TAKANO, Kenji Shizuka, Tomohiro Kusano, Jungmin Kim, Masato Kijima
  • Patent number: 8003476
    Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: August 23, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Naohiro Ueda, Masato Kijima
  • Patent number: 7871867
    Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having greater film thickness than the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 18, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Naohiro Ueda, Masato Kijima
  • Publication number: 20090215973
    Abstract: A propylenic polymer according to the present invention or a composition thereof have an excellent melt flowability and contains a less amount of stickiness-causing components, and also has a low modulus and is pliable, and is capable of providing a transparent molded article, thus being useful as a substitute for a pliable vinyl chloride resin. In addition, a molded article made therefrom exhibits an excellent heat seal performance at a low temperature, and is excellent in terms of transparency and rigidity. Specifically, it has an isotactic pentad fraction (mmmm), which indicates a stereoregularity, of 30 to 80%, a molecular weight distribution (Mw/Mn) of 3.5 or less and an intrinsic viscosity [?] of 0.8 to 5 dl/g.
    Type: Application
    Filed: April 23, 2009
    Publication date: August 27, 2009
    Applicant: Idemitsu Kosan Co., Ltd.
    Inventors: Yutaka Minami, Masato Kijima, Takuji Okamoto, Yasushi Seta, Yasuhiro Mogi, Tsuyoshi Ota, Hideo Funabashi, Takashi Kashiwamura, Noriyuki Tani, Masami Kanamaru, Koji Kakigami
  • Patent number: 7544758
    Abstract: A propylenic polymer according to the present invention or a composition thereof have an excellent melt flowability and contains a less amount of stickiness-causing components, and also has a low modulus and is pliable, and is capable of providing a transparent molded article, thus being useful as a substitute for a pliable vinyl chloride resin. In addition, a molded article made therefrom exhibits an excellent heat seal performance at a low temperature, and is excellent in terms of transparency and rigidity. Specifically, it has an isotactic pentad fraction (mmmm), which indicates a stereoregulariry, of 30 to 80%, a molecular weight distribution (Mw/Mn) of 3.5 or less and an intrinsic viscosity [?] of 0.8 to 5 dl/g.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: June 9, 2009
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Yutaka Minami, Masato Kijima, Takuji Okamoto, Yasushi Seta, Yasuhiro Mogi, Tsuyoshi Ota, Hideo Funabashi, Takashi Kashiwamura, Noriyuki Tani, Masami Kanamaru, Koji Kakigami
  • Patent number: 7504313
    Abstract: A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying a first well forming region and an alignment mark forming region using a first resist film as a mask for defining the first well forming region and the alignment mark forming region, implanting the first well forming region with a dopant of a first conductivity type and removing the first resist film, forming a second resist film to mask at least the first well forming region, having an opening overlying the alignment mark forming region larger than the opening of the selective etching film overlying the same region, and forming the alignment mark by performing an etching process using the second resist film and selective etching film as a mask.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: March 17, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Masato Kijima, Atsushi Harikai
  • Publication number: 20090067103
    Abstract: A high-frequency appliance, which is allowed to have an ESD tolerance by using a small-sized and low-cost ESD protection circuit, and in particular, an antenna duplexer having a multi-band high-frequency switch function. There are provided a signal separation unit for separating a first frequency band signal from a second frequency band signal, the second frequency band being lower than the first frequency band, a first SAW filter for inputting the first frequency band signal outputted from the signal separation unit, a second SAW filter for inputting the second frequency band signal outputted from the signal separation unit, and a high-pass filter for permitting passing of the second frequency band signal, and limiting passing of a signal whose frequency band is lower than the second frequency band, the high-pass filter being located on a signal line connecting the signal separation unit and the second SAW filter to each other.
    Type: Application
    Filed: April 26, 2006
    Publication date: March 12, 2009
    Inventors: Masato Kijima, Osamu Hikino, Takashi Shiba
  • Publication number: 20090068811
    Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.
    Type: Application
    Filed: November 14, 2008
    Publication date: March 12, 2009
    Applicant: RICOH COMPANY, LTD.
    Inventors: Naohiro UEDA, Masato Kijima
  • Patent number: 7476947
    Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 13, 2009
    Assignee: Ricoh Company, Ltd
    Inventors: Naohiro Ueda, Masato Kijima
  • Publication number: 20080268626
    Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 30, 2008
    Inventors: Masaaki Yoshida, Naohiro Ueda, Masato Kijima
  • Patent number: 7419893
    Abstract: This patent specification describes methods for fabricating semiconductor device having a plurality of well structures including a triple-well structure.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: September 2, 2008
    Inventor: Masato Kijima
  • Patent number: 7405460
    Abstract: A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 29, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Naohiro Ueda, Masato Kijima
  • Publication number: 20070215949
    Abstract: A disclosed semiconductor device includes: a semiconductor substrate; at least one normal transistor disposed on the semiconductor substrate; and at least one LOCOS offset transistor disposed on the semiconductor substrate. The normal transistor has an LDD region between a channel and a source and between the channel and a drain. And the LOCOS offset transistor has no LDD region between a channel and a source and between the channel and a drain.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 20, 2007
    Inventor: Masato Kijima
  • Patent number: 7199202
    Abstract: A propylenic polymer according to the present invention or a composition thereof have an excellent melt flowability and contains a less amount of stickiness-causing components, and also has a low modulus and is pliable, and is capable of providing a transparent molded article, thus being useful as a substitute for a pliable vinyl chloride resin. In addition, a molded article made therefrom exhibits an excellent heat seal performance at a low temperature, and is excellent in terms of transparency and rigidity. Specifically, it has an isotactic pentad fraction (mmmm), which indicates a stereoregulariry, of 30 to 80%, a molecular weight distribution (Mw/Mn) of 3.5 or less and an intrinsic viscosity [?] of 0.8 to 5 dl/g.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 3, 2007
    Assignee: Idemitsu Kosan Co. Ltd.
    Inventors: Yutaka Minami, Masato Kijima, Takuji Okamoto, Yasushi Seta, Yasuhiro Mogi, Tsuyoshi Ota, Hideo Funabashi, Takashi Kashiwamura, Noriyuki Tani, Masami Kanamaru, Koji Kakigami
  • Publication number: 20060293471
    Abstract: A propylenic polymer according to the present invention or a composition thereof have an excellent melt flowability and contains a less amount of stickiness-causing components, and also has a low modulus and is pliable, and is capable of providing a transparent molded article, thus being useful as a substitute for a pliable vinyl chloride resin. In addition, a molded article made therefrom exhibits an excellent heat seal performance at a low temperature, and is excellent in terms of transparency and rigidity. Specifically, it has an isotactic pentad fraction (mmmm), which indicates a stereoregulariry, of 30 to 80%, a molecular weight distribution (Mw/Mn) of 3.5 or less and an intrinsic viscosity [?] of 0.8 to 5 dl/g.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 28, 2006
    Applicant: Idemitsu Kosan Co., Ltd.
    Inventors: Yutaka Minami, Masato Kijima, Takuji Okamoto, Yasushi Seta, Yasuhiro Mogi, Tsuyoshi Ota, Hideo Funabashi, Takashi Kashiwamura, Noriyuki Tani, Masami Kanamaru, Koji Kakigami
  • Publication number: 20060216883
    Abstract: This patent specification describes methods for fabricating semiconductor device having a plurality of well structures including a triple-well structure.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 28, 2006
    Inventor: Masato Kijima
  • Publication number: 20060205139
    Abstract: A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying a first well forming region and an alignment mark forming region using a first resist film as a mask for defining the first well forming region and the alignment mark forming region, implanting the first well forming region with a dopant of a first conductivity type and removing the first resist film, forming a second resist film to mask at least the first well forming region, having an opening overlying the alignment mark forming region larger than the opening of the selective etching film overlying the same region, and forming the alignment mark by performing an etching process using the second resist film and selective etching film as a mask.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 14, 2006
    Inventors: Masato Kijima, Atsushi Harikai
  • Publication number: 20060197150
    Abstract: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.
    Type: Application
    Filed: February 22, 2006
    Publication date: September 7, 2006
    Inventors: Naohiro Ueda, Masato Kijima
  • Publication number: 20060188430
    Abstract: The invention provides a laminated film for stretch wrapping including at least three layers, wherein the laminated film has both surface layers containing, as a main component, component (A) which is an ethylene polymer, and has at least one intermediate layer formed of a layer containing, as a main component, a resin composition containing component (B) which is a polypropylene resin having controlled stereoregularity in terms of specific characteristics in an amount of 30 to 75% by weight; component (C) which is a crystalline polypropylene resin having a crystal melting peak temperature of 120° C. or higher in an amount of 20 to 60% by weight; and component (D) which is a petroleum resin in an amount of 5 to 30% by weight. The film of the present invention is excellent in storage stability of feed material pellets, wrapping efficiency, wrapping finish, elastic recovery, bottom sealing property, transparency, etc.
    Type: Application
    Filed: July 22, 2003
    Publication date: August 24, 2006
    Applicant: MITSUBISHI PLASTICS, INC.
    Inventors: Kouichirou Taniguchi, Hideki Sasaki, Masato Kijima