Patents by Inventor Masato Koyama
Masato Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7737503Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.Type: GrantFiled: March 19, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Masato Koyama, Masahiko Yoshiki
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Patent number: 7727832Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.Type: GrantFiled: October 11, 2007Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Seiji Inumiya
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Patent number: 7728394Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.Type: GrantFiled: September 10, 2008Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Patent number: 7718521Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.Type: GrantFiled: June 5, 2008Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
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Publication number: 20100078731Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.Type: ApplicationFiled: December 7, 2009Publication date: April 1, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori TSUCHIYA, Masato KOYAMA, Masahiko YOSHIKI
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Patent number: 7667273Abstract: A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.Type: GrantFiled: February 27, 2007Date of Patent: February 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya
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Publication number: 20100035392Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.Type: ApplicationFiled: August 27, 2009Publication date: February 11, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Masato Koyama
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Publication number: 20100032765Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.Type: ApplicationFiled: August 27, 2009Publication date: February 11, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori TSUCHIYA, Masato Koyama
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Patent number: 7646072Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: GrantFiled: January 22, 2009Date of Patent: January 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Publication number: 20090321844Abstract: A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.Type: ApplicationFiled: June 25, 2009Publication date: December 31, 2009Inventors: Reika Ichihara, Masato Koyama
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Publication number: 20090317951Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.Type: ApplicationFiled: September 4, 2009Publication date: December 24, 2009Inventors: Reika Ichihara, Yoshinori Tsuchiya, Hiroki Tanaka, Masato Koyama
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Patent number: 7632728Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.Type: GrantFiled: September 10, 2008Date of Patent: December 15, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Patent number: 7612413Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.Type: GrantFiled: August 1, 2006Date of Patent: November 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Publication number: 20090267134Abstract: A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, having sites that perform electron trapping and releasing and are formed by adding an element different from a base material, and including insulating layers having different dielectric constants, the sites having a higher level than a Fermi level of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.Type: ApplicationFiled: September 18, 2008Publication date: October 29, 2009Inventors: Masahiro Koike, Yuuichiro Mitani, Yasushi Nakasaki, Masato Koyama
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Publication number: 20090267159Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.Type: ApplicationFiled: February 19, 2009Publication date: October 29, 2009Inventors: Kosuke Tstsumura, Masakazu Goto, Reika Ichihara, Masato Koyama, Shigeru Kawanaka, Kazuaki Nakajima
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Patent number: 7608896Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.Type: GrantFiled: September 18, 2007Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Hiroki Tanaka, Masato Koyama
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Patent number: 7608849Abstract: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10 times or greater change in electric resistance with a temperature change within a range of ±80 K from a predetermined temperature; a Peltier element causing the switching film to have the temperature change; a heat conducting/electric insulating film provided between the switching film and the Peltier element, to conduct heat from the Peltier element; and a pair of electrodes connected to the switching film.Type: GrantFiled: October 31, 2006Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Masato Koyama
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Publication number: 20090263950Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.Type: ApplicationFiled: June 25, 2009Publication date: October 22, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
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Patent number: 7601623Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.Type: GrantFiled: July 16, 2008Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Masato Koyama
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Publication number: 20090242970Abstract: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.Type: ApplicationFiled: February 19, 2009Publication date: October 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Masato Koyama