Patents by Inventor Masato Shimada

Masato Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10974912
    Abstract: A method for transferring a plurality of columnar honeycomb structures according to the present invention includes: subjecting first side surfaces of the plurality of columnar honeycomb structures to vacuum suction; and correctively transferring the plurality of the columnar honeycomb structures, optionally while supporting second side surfaces opposing to the first side surfaces of the plurality of columnar honeycomb structures by a supporting member.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 13, 2021
    Assignee: NGK Insulators, Ltd.
    Inventors: Chikashi Ihara, Masato Shimada, Shinya Yoshida
  • Publication number: 20200309454
    Abstract: A method for manufacturing a ceramic product containing silicon carbide, including a step of firing a formed body of a green body containing silicon carbide by transporting the formed body from an inlet to an outlet of a continuous furnace, wherein the continuous furnace includes the inlet, a heating zone, a cooling zone, and the outlet in this order, and a furnace atmosphere in both the heating zone and the cooling zone is an inert gas having an oxygen concentration of 100 ppm by volume or less.
    Type: Application
    Filed: March 23, 2020
    Publication date: October 1, 2020
    Applicant: NGK Insulators, LTD.
    Inventors: Yoshiyuki Kamei, Chikashi Ihara, Masato Shimada, Kazuhi Matsumoto
  • Patent number: 10573463
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 25, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Ichiro Asaoka, Koichi Morozumi, Masato Shimada, Akira Kuriki
  • Publication number: 20190218150
    Abstract: A method of producing a ceramic fired body may includes a step of passing a first accommodating shelf through a firing kiln, the first accommodating shelf including a stack of units of a shelf plate and a frame placed on the shelf plate, one or more ceramic bodies placed on the shelf plate being surrounded by the frame extending in a circumferential direction between the shelf plates; a step of retrieving one or more frames from the first accommodating shelf which has passed through the firing kiln; a step of using the one or more retrieved frames to build a second accommodating shelf for passing through the firing kiln; and a step of rotating the retrieved frame such that a rotational position of the retrieved frame when the second accommodating shelf passes through the firing kiln is different from a rotational position of the retrieved frame when the first accommodating shelf passed through the firing kiln.
    Type: Application
    Filed: December 24, 2018
    Publication date: July 18, 2019
    Applicant: NGK INSULATORS, LTD.
    Inventors: Chikashi IHARA, Shinya YOSHIDA, Yoshiyuki KAMEI, Masato SHIMADA
  • Publication number: 20190177096
    Abstract: A method for transferring a plurality of columnar honeycomb structures according to the present invention includes: subjecting first side surfaces of the plurality of columnar honeycomb structures to vacuum suction; and correctively transferring the plurality of the columnar honeycomb structures, optionally while supporting second side surfaces opposing to the first side surfaces of the plurality of columnar honeycomb structures by a supporting member.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 13, 2019
    Applicant: NGK INSULATORS, LTD.
    Inventors: Chikashi IHARA, Masato Shimada, Shinya Yoshida
  • Patent number: 10272685
    Abstract: A method is provided for manufacturing a piezoelectric device including a piezoelectric element that is disposed above a diaphragm and that has a multilayer structure including a first electrode disposed above the diaphragm, a piezoelectric layer disposed on the first electrode, and a second electrode disposed on the piezoelectric layer. The method includes forming the multilayer structure including the first electrode, the piezoelectric layer, and the second electrode above the diaphragm, forming a voltage application electrode extending outwardly from an end of the second electrode to cover a region located above the piezoelectric layer in an inactive section having no second electrode, applying a voltage between the first electrode and the second electrode, and removing the voltage application electrode.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Yuma Fukuzawa, Shunya Fukuda, Masato Shimada, Mutsuhiko Ota
  • Publication number: 20190051461
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Ichiro ASAOKA, Koichi MOROZUMI, Masato SHIMADA, Akira KURIKI
  • Patent number: 10134527
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 20, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Ichiro Asaoka, Koichi Morozumi, Masato Shimada, Akira Kuriki
  • Publication number: 20180265419
    Abstract: A manufacturing method of a silicon carbide-based honeycomb structure, including a firing step of introducing extruded honeycomb formed bodies containing a silicon carbide-based component, together with firing members into a firing furnace, and firing the honeycomb formed bodies, to manufacture the silicon carbide-based honeycomb structure, wherein the firing members are formed by using a ceramic material containing 70 wt % or more of alumina, and the firing step further includes: an inert gas supplying step of supplying an inert gas to a furnace space of the firing furnace, and a gas adding step of adding a reducing gas to the furnace space.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 20, 2018
    Applicant: NGK INSULATORS, LTD.
    Inventors: Chikashi IHARA, Shinya YOSHIDA, Masato SHIMADA, Yoshiyuki KAMEI
  • Publication number: 20180065364
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 8, 2018
    Inventors: Ichiro ASAOKA, Koichi MOROZUMI, Masato SHIMADA, Akira KURIKI
  • Patent number: 9840077
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 12, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Ichiro Asaoka, Koichi Morozumi, Masato Shimada, Akira Kuriki
  • Publication number: 20170266970
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Ichiro ASAOKA, Koichi MOROZUMI, Masato SHIMADA, Akira KURIKI
  • Publication number: 20170217182
    Abstract: A method is provided for manufacturing a piezoelectric device including a piezoelectric element that is disposed above a diaphragm and that has a multilayer structure including a first electrode disposed above the diaphragm, a piezoelectric layer disposed on the first electrode, and a second electrode disposed on the piezoelectric layer. The method includes forming the multilayer structure including the first electrode, the piezoelectric layer, and the second electrode above the diaphragm, forming a voltage application electrode extending outwardly from an end of the second electrode to cover a region located above the piezoelectric layer in an inactive section having no second electrode, applying a voltage between the first electrode and the second electrode, and removing the voltage application electrode.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 3, 2017
    Inventors: Yuma FUKUZAWA, Shunya FUKUDA, Masato SHIMADA, Mutsuhiko OTA
  • Patent number: 9694580
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 4, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Ichiro Asaoka, Koichi Morozumi, Masato Shimada, Akira Kuriki
  • Publication number: 20170057230
    Abstract: An electronic device includes a capacitor that is configured with a first electrode layer, an insulating layer, and a second electrode layer being formed in the order listed herein. At least one end of the capacitor is defined by an end of the second electrode layer. The insulating layer is provided so as to extend to a non-element region that is on the outside of one end of the capacitor. The insulating layer under the non-element region is formed thinner than the insulating layer under the capacitor. A difference between the thickness of the insulating layer under the non-element region and the thickness of the insulating layer under the capacitor is equal to or less than 50 nm.
    Type: Application
    Filed: August 18, 2016
    Publication date: March 2, 2017
    Inventors: Ichiro ASAOKA, Koichi MOROZUMI, Masato SHIMADA, Akira KURIKI
  • Patent number: 8966729
    Abstract: In sputter etching to improve the adhesion between upper electrodes and lead electrodes, the sputter etching of surfaces of the upper electrodes under an Ar gas flow at a flow rate of 60 sccm or more can reduce the residence time of Ar ions on the surfaces of the upper electrodes because of the Ar gas flow. This can prevent the charging of the upper electrodes due to the buildup of ionized Ar gas on the surfaces, reduce the influence of charging on piezoelectric elements, and provide a method for manufacturing a piezoelectric actuator that includes the piezoelectric elements each including a piezoelectric layer having small variations in hysteresis characteristics and deformation characteristics.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 3, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hironobu Kazama, Takahiro Kamijo, Masato Shimada, Hiroyuki Kamei, Yuka Yonekura, Motoki Takabe
  • Patent number: 8632167
    Abstract: A piezoelectric element includes a first electrode which is an individual electrode, a piezoelectric layer, and a second electrode which is a common electrode. The piezoelectric element is provided with a piezoelectric active section and a piezoelectric nonactive section so as to face the pressure generating chambers. The piezoelectric nonactive section extends to the outside of the pressure generating chambers. On the piezoelectric layer of the piezoelectric nonactive section, a stress controlling layer is provided which has the same direction of internal stress as internal stress of the second electrode and is electrically insulated from the second electrode.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 21, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Masato Shimada
  • Patent number: 8622528
    Abstract: A first lead electrode containing nickel and chromium contacts a second upper electrode containing titanium. Here, since a difference between the normal electrode potential of nickel and chromium and the normal electrode potential of titanium is smaller than a difference between the normal electrode potential of nickel and chromium and the normal electrode potential of iridium, electric corrosion can be made difficult to occur as compared with the case where the first lead electrode containing nickel and chromium contacts a first upper electrode containing iridium. Therefore, a piezoelectric element can be obtained in which an increase in resistance due to the narrowing of the contact area between an upper electrode and a lead electrode for upper electrode or the separation of the lead electrode for upper electrode can be suppressed and which can be driven by a given voltage.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: January 7, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Masato Shimada
  • Patent number: 8591011
    Abstract: A piezoelectric element includes a lower electrode film disposed on a substrate, a piezoelectric layer 70 disposed on the lower electrode film, a upper electrode film 80 disposed on the piezoelectric layer 70, wherein the piezoelectric layer 70 is formed of a plurality of columnar grains 70a, and the upper electrode film 80 conforms to the surface shape of each of the grains 70a of the piezoelectric layer 70.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Masato Shimada, Xin-shan Li
  • Patent number: 8366248
    Abstract: A piezoelectric element includes a lower electrode film disposed on a substrate, a piezoelectric layer 70 disposed on the lower electrode film, a upper electrode film 80 disposed on the piezoelectric layer 70, wherein the piezoelectric layer 70 is formed of a plurality of columnar grains 70a, and the upper electrode film 80 conforms to the surface shape of each of the grains 70a of the piezoelectric layer 70.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 5, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Masato Shimada, Xin-Shan Li