Patents by Inventor Masatomi Harada

Masatomi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11316061
    Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Tokuaki Kuniyoshi, Liumin Zou
  • Publication number: 20220084754
    Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
  • Patent number: 11271074
    Abstract: A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takeshi Kagawa, Masatomi Harada
  • Publication number: 20220059290
    Abstract: A capacitor that includes a substrate having a surface; a lower electrode opposing the surface of the substrate; a dielectric film on the lower electrode; an upper electrode on the dielectric film; a protective layer on the lower electrode, the dielectric film, and the upper electrode, the protective layer defining a through-hole exposing at least one of the lower electrode and the upper electrode; at least one protrusion in the through-hole; and an outer electrode covering the through-hole and the at least one protrusion.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Inventors: Hiroshi Matsubara, Masatomi Harada, Takeshi Kagawa
  • Publication number: 20220059646
    Abstract: A capacitor that includes a substrate; a capacitor structure including a lower electrode on the substrate, a dielectric film on the lower electrode and having a via hole, and an upper electrode on the dielectric film; a first terminal electrode in the via hole and electrically connected to the lower electrode; and a second terminal electrode electrically connected to the upper electrode. The width of the via hole of the dielectric film is less than or equal to twice the film thickness of the first terminal electrode.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Inventors: Takeshi Kagawa, Masatomi Harada, Hiroshi Matsubara
  • Patent number: 11232911
    Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 25, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
  • Patent number: 11227966
    Abstract: Provided is a photoelectric conversion device capable of suppressing diffusion of a dopant in a p layer or n layer into an adjacent layer. A photoelectric conversion device is provided with a silicon substrate, a substantially intrinsic amorphous layer formed on one surface of the silicon substrate, and a first conductive amorphous layer that is formed on the intrinsic amorphous layer. The first conductive amorphous layer includes a first concentration layer and a second concentration layer that is stacked on the first concentration layer. The dopant concentration of the second concentration layer is 8×1017 cm?3 or more, and is lower than the dopant concentration of the first concentration layer.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: January 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masatomi Harada, Toshihiko Sakai, Rihito Suganuma, Kazuya Tsujino, Tokuaki Kuniyoshi, Takeshi Kamikawa
  • Patent number: 11217395
    Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: January 4, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
  • Patent number: 11101072
    Abstract: A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 24, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Nobuhiro Ishida
  • Publication number: 20210050467
    Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).
    Type: Application
    Filed: October 15, 2020
    Publication date: February 18, 2021
    Inventors: Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Tokuaki Kuniyoshi, Liumin Zou
  • Publication number: 20210027951
    Abstract: A plurality of capacitors and a holding body constructed to hold the plurality of capacitors. Each of the plurality of capacitors includes a semiconductor substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an outer electrode. Among a first capacitor and a second capacitor of the plurality of capacitors, the second capacitor has a shape different from a shape of the first capacitor in at least one of the first electrode layer, the second electrode layer, and the outer electrode.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 28, 2021
    Inventors: Masatomi Harada, Masaki Takeuchi, Takeshi Kagawa, Hiroshi Matsubara
  • Publication number: 20210020738
    Abstract: A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: Takeshi Kagawa, Masatomi Harada
  • Patent number: 10658526
    Abstract: In a photovoltaic device (1), first amorphous semiconductor portions (102n) and second amorphous semiconductor portions (102p) are provided alternately on one of faces of a semiconductor substrate (101). Each first amorphous semiconductor portion (102n) has at least one first amorphous semiconductor strip (1020n), and each second amorphous semiconductor portion (102p) has at least one second amorphous semiconductor strip (1020p). A plurality of first electrodes (103n) are provided spaced apart from each other on each first amorphous semiconductor strip (1020n), and a plurality of second electrodes (103p) are provided spaced apart from each other on each second amorphous semiconductor strip (1020p).
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masatomi Harada, Kenichi Higashi, Takeshi Kamikawa, Toshihiko Sakai, Tokuaki Kuniyoshi, Kazuya Tsujino, Liumin Zou
  • Publication number: 20200082989
    Abstract: A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Hiroshi Matsubara, Nubuhiro Ishida
  • Patent number: 10505064
    Abstract: A photovoltaic device and a photovoltaic module are provided that suppressing diffusion of boron and thereby improving conversion efficiency. A photovoltaic device 10 includes: a semiconductor substrate 1; an intrinsic amorphous semiconductor layer 3 provided on the semiconductor substrate 1; n-type amorphous semiconductor strips 4 containing phosphorus as a dopant; and p-type amorphous semiconductor strips 5 containing boron as a dopant, the n- and p-type amorphous semiconductor strips 4 and 5 being provided alternately on the intrinsic amorphous semiconductor layer 3 as viewed along an in-plane direction. Each n-type amorphous semiconductor strip 4 includes a reduced-thickness region TD(n) on a face thereof adjacent to one of the p-type amorphous semiconductor strips 5. Each p-type amorphous semiconductor strip 5 includes a reduced-thickness region TD(p) on a face thereof adjacent to one of the n-type amorphous semiconductor strips 4.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 10, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tokuaki Kuniyoshi, Kenichi Higashi, Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Kazuya Tsujino, Liumin Zou
  • Publication number: 20190311854
    Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
  • Publication number: 20190244761
    Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Nobuhiro Ishida
  • Publication number: 20190244762
    Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
  • Patent number: 10355145
    Abstract: A photovoltaic device (1) includes: an i-type amorphous semiconductor layer (102i) formed in contact with one of the surfaces of a semiconductor substrate (101); p-type amorphous semiconductor strips (102p) spaced apart from each other and provided on the i-type amorphous semiconductor layer (102i); and n-type amorphous semiconductor strips (102n) spaced apart from each other and provided on the i amorphous semiconductor layer (102i), each n-type amorphous semiconductor strip (102n) being adjacent to at least one of the p-type amorphous semiconductor strips (102p) as traced along an in-plane direction of the semiconductor substrate (101). The photovoltaic device (1) further includes electrodes (103) as a protection layer formed in contact with the i-type amorphous semiconductor layer (102) between adjacent p-type amorphous semiconductor strips (102p) and between adjacent n-type amorphous semiconductor strips (102n).
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: July 16, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masatomi Harada, Kenichi Higashi, Takeshi Kamikawa, Toshihiko Sakai, Tokuaki Kuniyoshi, Kazuya Tsujino, Liumin Zou
  • Patent number: 10293368
    Abstract: A film-forming method for forming a thin film on a substrate includes a contact step, an external force removal step, and a film-forming step. At the contact step (step B), the substrate 30 and a member 31 in contact with one surface of the substrate is stacked, and the substrate 30 and the member 31 in contact with one surface of the substrate are placed under vacuum while an external force is applied in a direction in which the substrate 30 and the member 31 in contact with one surface of the substrate are stacked. At the external force removal step (step C), the external force is removed at atmospheric pressure or under vacuum. At a film-forming step (step E), a thin film is formed on the one surface or the other surface of the substrate 30.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 21, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Toshihiko Sakai, Takeshi Kamikawa, Masatomi Harada, Tokuaki Kuniyoshi, Liumin Zou