Patents by Inventor Masatomi Harada
Masatomi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072107Abstract: A semiconductor device that includes a substrate; a first electrode layer on the substrate; a dielectric film on the first electrode layer; a second electrode layer on the dielectric film; a protective layer covering the first electrode layer and the second electrode layer; and an outer electrode penetrating the protective layer. The dielectric film includes silicon nitride, and an atomic concentration ratio of Si to a total amount of Si and N contained in the dielectric film is 43 atom % to 70 atom %.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: Masatomi HARADA, Korekiyo ITO, Takeshi KAGAWA
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Publication number: 20240071687Abstract: A semiconductor device that includes: a substrate having a first main surface and a second main surface opposite to each other in a thickness direction; a circuit layer on the first main surface of the substrate, the circuit layer having a first electrode layer, a second electrode layer, a dielectric layer between the first electrode layer and the second electrode layer, a first outer electrode and a second outer electrode each extending to a surface of the circuit layer opposite to the substrate; and a first resin body at each of four corners of the substrate in a plan view in the thickness direction, and wherein, in the thickness direction, a top end of the first resin body on the side opposite to the substrate is positioned higher than top ends of the first outer electrode and the second outer electrode on the side opposite to the substrate.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: Korekiyo ITO, Masatomi HARADA, Yuta IMAMURA
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Publication number: 20240063224Abstract: A support substrate for a passive electronic component, the support substrate including: a semiconductor substrate; a charge trap layer on the semiconductor substrate and having a higher crystal defect density than the semiconductor substrate; and an insulating layer on the charge trap layer. In a first aspect, the insulating layer is composed of silicon nitride, and an atomic concentration ratio of N to a total amount of Si and N in the insulating layer is not greater than 45 atom %. In a second aspect, the insulating layer includes a first insulating layer on the charge trap layer; and a second insulating layer on the first insulating layer, wherein a first fixed charge within the first insulating layer and a second fixed charge within the second insulating layer have opposite polarities, and the first insulating layer has a thickness of not less than 0.5 nm and not greater than 3 nm.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Korekiyo ITO, Masatomi HARADA
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Publication number: 20240062958Abstract: A capacitor that includes: a substrate; a first electrode layer on the substrate, the first electrode layer including a first principal surface facing the substrate, and a second principal surface opposite the first principal surface; a dielectric film on the first electrode layer and covering an end portion of the first electrode layer; a second electrode layer on the dielectric film, the second electrode layer including a third principal surface facing the dielectric film, a fourth principal surface opposite the third principal surface, and a side surface joining the third principal surface and the fourth principal surface, wherein at least part of the side surface of the second electrode layer has a tapered shape which is inclined inward from the third principal surface to the fourth principal surface.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Masatomi HARADA, Korekiyo ITO, Takeshi KAGAWA, Yuta IMAMURA
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Publication number: 20240063252Abstract: A semiconductor device that includes: a substrate having a first main surface and a second main surface opposite to each other in a thickness direction; a circuit layer on the first main surface of the substrate; and a first resin body between an end portion of the substrate and the first outer electrode, and between the end portion of the substrate and the second outer electrode in a plan view in the thickness direction. In the thickness direction, a leading end of the first resin body is positioned higher than top ends of the first and second outer electrodes. In a sectional view, a first side surface of the first resin body approaches a second side surface of the first resin body on a side close to the end portion of the substrate, and the second side surface rises steeply against a first main surface of the substrate.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Yuta IMAMURA, Masatomi HARADA, Takeshi KAGAWA, Korekiyo ITO
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Patent number: 11587738Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: GrantFiled: November 29, 2021Date of Patent: February 21, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11545304Abstract: A plurality of capacitors and a holding body constructed to hold the plurality of capacitors. Each of the plurality of capacitors includes a semiconductor substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an outer electrode. Among a first capacitor and a second capacitor of the plurality of capacitors, the second capacitor has a shape different from a shape of the first capacitor in at least one of the first electrode layer, the second electrode layer, and the outer electrode.Type: GrantFiled: October 13, 2020Date of Patent: January 3, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Masaki Takeuchi, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11521800Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.Type: GrantFiled: April 16, 2019Date of Patent: December 6, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Nobuhiro Ishida
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Publication number: 20220376036Abstract: A semiconductor device is provided that includes a substrate 10 with first and second opposing main surfaces, a circuit layer disposed on the first main surface, and a first resin body on a surface of the circuit layer opposite from the substrate. The circuit layer includes first and second electrode layers on a side of the semiconductor substrate, a dielectric layer disposed between the electrode layers, a first outer electrode electrically connected to the first electrode layer and extended to the surface of the circuit layer, and a second outer electrode electrically connected to the second electrode layer and extended to the surface of the circuit layer. The first resin body is between the first and second outer electrodes in a plan view, and in sectional view, a tip end of the first resin body is positioned higher than tip ends of the first and second outer electrodes.Type: ApplicationFiled: August 3, 2022Publication date: November 24, 2022Inventors: Hiroshi MATSUBARA, Masatomi HARADA, Takeshi KAGAWA
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Publication number: 20220336345Abstract: A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.Type: ApplicationFiled: July 7, 2022Publication date: October 20, 2022Inventors: Masatomi HARADA, Takeshi KAGAWA, Hiroshi MATSUBARA, Nobuyoshi ADACHI
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Publication number: 20220336155Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces that oppose each other in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer includes a first electrode layer on a side of the semiconductor substrate, a second electrode layer that faces the first electrode layer, a dielectric layer disposed between the electrode layers, and a first outer electrode electrically connected to the first electrode layer through an opening in the dielectric layer. An end portion of the dielectric layer on a side of the first region is in contact with the first electrode layer, and in the dielectric layer, a size of the end portion in the thickness direction is smaller than a size of an inter-electrode portion between the first and second electrode layers in the thickness direction.Type: ApplicationFiled: July 7, 2022Publication date: October 20, 2022Inventors: Takeshi KAGAWA, Masatomi HARADA, Hiroshi MATSUBARA
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Patent number: 11476055Abstract: A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.Type: GrantFiled: November 13, 2019Date of Patent: October 18, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Hiroshi Matsubara, Nobuhiro Ishida
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Patent number: 11316061Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).Type: GrantFiled: October 15, 2020Date of Patent: April 26, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Tokuaki Kuniyoshi, Liumin Zou
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Publication number: 20220084754Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11271074Abstract: A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.Type: GrantFiled: September 30, 2020Date of Patent: March 8, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takeshi Kagawa, Masatomi Harada
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Publication number: 20220059290Abstract: A capacitor that includes a substrate having a surface; a lower electrode opposing the surface of the substrate; a dielectric film on the lower electrode; an upper electrode on the dielectric film; a protective layer on the lower electrode, the dielectric film, and the upper electrode, the protective layer defining a through-hole exposing at least one of the lower electrode and the upper electrode; at least one protrusion in the through-hole; and an outer electrode covering the through-hole and the at least one protrusion.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventors: Hiroshi Matsubara, Masatomi Harada, Takeshi Kagawa
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Publication number: 20220059646Abstract: A capacitor that includes a substrate; a capacitor structure including a lower electrode on the substrate, a dielectric film on the lower electrode and having a via hole, and an upper electrode on the dielectric film; a first terminal electrode in the via hole and electrically connected to the lower electrode; and a second terminal electrode electrically connected to the upper electrode. The width of the via hole of the dielectric film is less than or equal to twice the film thickness of the first terminal electrode.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Takeshi Kagawa, Masatomi Harada, Hiroshi Matsubara
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Patent number: 11232911Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.Type: GrantFiled: April 17, 2019Date of Patent: January 25, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
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Patent number: 11227966Abstract: Provided is a photoelectric conversion device capable of suppressing diffusion of a dopant in a p layer or n layer into an adjacent layer. A photoelectric conversion device is provided with a silicon substrate, a substantially intrinsic amorphous layer formed on one surface of the silicon substrate, and a first conductive amorphous layer that is formed on the intrinsic amorphous layer. The first conductive amorphous layer includes a first concentration layer and a second concentration layer that is stacked on the first concentration layer. The dopant concentration of the second concentration layer is 8×1017 cm?3 or more, and is lower than the dopant concentration of the first concentration layer.Type: GrantFiled: April 3, 2015Date of Patent: January 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masatomi Harada, Toshihiko Sakai, Rihito Suganuma, Kazuya Tsujino, Tokuaki Kuniyoshi, Takeshi Kamikawa
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Patent number: 11217395Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: GrantFiled: June 21, 2019Date of Patent: January 4, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara