Patents by Inventor Masatoshi Ishii

Masatoshi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962946
    Abstract: There is provided with an image processing apparatus that generates a display image to be displayed in a display system including a display area. An obtaining unit obtains one input image acquired through shooting by one image capturing apparatus. A generating unit generates the display image from the input image on the basis of a correspondence between a first projection plane corresponding to the input image and a second projection plane corresponding to the display area.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 16, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masatoshi Ishii
  • Publication number: 20240111244
    Abstract: An image forming apparatus, having a main housing, a first photosensitive drum, a second photosensitive drum, a first developing device to supply toner to the first photosensitive drum, a second developing device to supply toner to the second photosensitive drum, a first reloading device to reload the first developing device with the toner, and a second reloading device to reload the second developing device with the toner, is provided. The first reloading device has a first reloading port, which accepts the toner for reloading the first developing device. The first reloading port is openable to an outside of the main housing. The second reloading device has a second reloading port, which accepts the toner for reloading the second developing device. The second reloading port is openable to the outside of the main housing.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventors: Yasutada KATO, Shunsuke ISHII, Masatoshi SHIRAKI, Shougo SATO
  • Publication number: 20230393795
    Abstract: An image processing apparatus includes an image acquisition unit configured to acquire a first thumbnail image having a first angle of view recorded in an image file, an image generation unit configured to generate a second thumbnail image having a second angle of view different from the first angle of view, an image setting unit configured to set a thumbnail image to be displayed in a thumbnail display area depending on whether a cursor operated by a user is located in the thumbnail display area on a screen, and a display unit configured to display a thumbnail image set by the image setting unit in the thumbnail display area on the screen, wherein, in a case where a cursor is located in the thumbnail display area on the screen, the image setting unit sets the second thumbnail image as a thumbnail image to be displayed in the thumbnail display area.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 7, 2023
    Inventor: MASATOSHI ISHII
  • Publication number: 20230388475
    Abstract: The technique disclosed herein makes it possible to save a proper screenshot, i.e., images with display angles of view of an HMD, and also enable one to check a situation even outside the display angles of view at the time of saving the screenshot. When receiving a notification that a screen capture command is received from a command receiver, an image file generator acquires wide angle images from a wide angle image generator, acquires display angle-of-view information from a display image generator, sets the wide angle images as image data to be stored in a main image region of an image file, sets the acquired display angle-of-view information as data to be stored in a metadata region of the image file, generates an image file of a screenshot according to the settings, and saves the image file in an HDD.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 30, 2023
    Inventor: MASATOSHI ISHII
  • Publication number: 20230385619
    Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Atsuya Okazaki, Masatoshi Ishii, Junka Okazawa, Kohji Hosokawa, Takayuki Osogami
  • Patent number: 11823740
    Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan, Paul Michael Solomon
  • Publication number: 20230297821
    Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 21, 2023
    Inventors: Masatoshi Ishii, Takeo Yasuda
  • Patent number: 11763139
    Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Atsuya Okazaki, Masatoshi Ishii, Junka Okazawa, Kohji Hosokawa, Takayuki Osogami
  • Patent number: 11741353
    Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 29, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Masatoshi Ishii, Takeo Yasuda
  • Publication number: 20230198511
    Abstract: A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan
  • Publication number: 20230178150
    Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan, Paul Michael Solomon
  • Patent number: 11562717
    Abstract: An image processing apparatus is described comprising a first acquisition unit configured to acquire image data from an image capturing apparatus and a second acquisition unit configured to acquire display installation information indicating a configuration of one or more display screens in a display installation to be simulated. A generation unit is provided to generate, based on the display installation information and the acquired image data, a simulation image that simulates display of the image on the display installation. A display control unit is provided to display the simulation image on a display device.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 24, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masatoshi Ishii
  • Publication number: 20220318977
    Abstract: An image processing apparatus is configured to determine presence or absence of print abnormality in a target image by comparing a reference image or reference images, each of which is a print result to be a reference, and the target image, which is a print result to be an inspection target. The image processing apparatus includes a setting unit configured to set an inspection condition for a printed product, and a comparison unit configured to compare the reference image or reference images and the target image using a number of the reference images set based on the inspection condition.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 6, 2022
    Inventor: Masatoshi Ishii
  • Publication number: 20220191339
    Abstract: In an image processing apparatus, a condition for detecting a print position deviation on a print medium in a printed material is set. Based on the condition, data obtained by reading the print medium for the print position deviation is inspected. In the condition, in a case where a width of the print medium is larger than a readable width for reading the print medium, a settable range is small relative to a case where the width of the print medium is smaller than the readable width.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 16, 2022
    Inventor: Masatoshi Ishii
  • Publication number: 20220180165
    Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Masatoshi Ishii, Takeo Yasuda
  • Patent number: 11321608
    Abstract: A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Takeo Yasuda, Masatoshi Ishii
  • Patent number: 11270191
    Abstract: A spiking neural network device including a spiking neural network circuit including a crossbar array of plural synapses; plural axons connected with the spiking neural network circuit, the plural axons receiving input of a spike signal; and plural Poisson spike generators respectively provided for the plural axons. Each Poisson spike generator can be set whether or not to emit the spike signal based on an input signal to be processed, and each Poisson spike generator can, be set to emit the spike signal being configured to generate a Poisson spike train different from each other. and supply the Poisson spike train to a corresponding one of the plural axons.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Junka Okazawa, Masatoshi Ishii, Atsuya Okazaki, Kohji Hosokawa
  • Publication number: 20210256941
    Abstract: An image processing apparatus is described comprising a first acquisition unit configured to acquire image data from an image capturing apparatus and a second acquisition unit configured to acquire display installation information indicating a configuration of one or more display screens in a display installation to be simulated. A generation unit is provided to generate, based on the display installation information and the acquired image data, a simulation image that simulates display of the image on the display installation. A display control unit is provided to display the simulation image on a display device.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 19, 2021
    Inventor: Masatoshi Ishii
  • Patent number: 11023805
    Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Atsuya Okazaki, Junka Okazawa, Takayuki Osogami
  • Patent number: 11024265
    Abstract: An image processing apparatus is described comprising a first acquisition unit configured to acquire image data from an image capturing apparatus and a second acquisition unit configured to acquire display installation information indicating a configuration of one or more display screens in a display installation to be simulated. A generation unit is provided to generate, based on the display installation information and the acquired image data, a simulation image that simulates display of the image on the display installation. A display control unit is provided to display the simulation image on a display device.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masatoshi Ishii