Patents by Inventor Masatoshi Ishii
Masatoshi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250110445Abstract: An image forming apparatus, having a main housing, a first photosensitive drum, a second photosensitive drum, a first developing device to supply toner to the first photosensitive drum, a second developing device to supply toner to the second photosensitive drum, a first reloading device to reload the first developing device with the toner, and a second reloading device to reload the second developing device with the toner, is provided. The first reloading device has a first reloading port, which accepts the toner for reloading the first developing device. The first reloading port is openable to an outside of the main housing. The second reloading device has a second reloading port, which accepts the toner for reloading the second developing device. The second reloading port is openable to the outside of the main housing.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Yasutada KATO, Shunsuke ISHII, Masatoshi SHIRAKI, Shougo SATO
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Publication number: 20250103774Abstract: A system for implementing a row-by-row convolution neural network using an in-memory compute architecture. A controller is configured to manage generation of a plurality of output images. A filter memory is configured to store copies of each of a plurality of sets of image filters. A plurality of multiply-accumulate crossbar arrays is configured for the parallel computation of elements of the given row for each of the plurality of output images. A plurality of sets of steering circuits is coupled to a bank of capacitors and configured to steer currents generated by the plurality of multiply-accumulate crossbar arrays to corresponding capacitors of the bank of capacitors. A plurality of sets of comparator circuits are configured to pulse-width modulate a signal based on a voltage of a corresponding capacitor of the bank of capacitors. Peripheral circuitry is configured to output elements of the plurality of output images via pulse-width modulated signals.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Pritish Narayanan, Geoffrey Burr, Masatoshi Ishii, HsinYu Tsai
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Patent number: 12255656Abstract: A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.Type: GrantFiled: December 17, 2021Date of Patent: March 18, 2025Assignee: International Business Machines CorporationInventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan
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Patent number: 12233894Abstract: An occupant state detection system includes an occupant monitoring apparatus, an occupant state detection apparatus, and a determination apparatus. The occupant state detection apparatus includes one or more processors and one or more memories. The one or more processors cooperate with one or more programs included in the one or more memories to receive occupant monitoring data from the occupant monitoring apparatus and determination data from the determination apparatus. On the basis of the determination data, the one or more processors make assignment of a part to be monitored, of an occupant in a vehicle, to be monitored by the occupant monitoring apparatus, to detect a physical state of the occupant.Type: GrantFiled: March 18, 2022Date of Patent: February 25, 2025Assignee: SUBARU CORPORATIONInventors: Ryota Nakamura, Tsukasa Mikuni, Takuya Homma, Yutaka Ishii, Masatoshi Tsuge, Kazuhiro Hayakawa, Toru Kato
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Publication number: 20250053838Abstract: A non-transitory computer-readable recording medium storing a quantum circuit design program for causing a computer to execute processing including: detecting a first quantum gate of which a gate operation is not performed by a quantum device, from a quantum circuit that indicates a gate operation on a plurality of qubits included in the quantum device; determining an equivalent circuit to be mounted, from among a plurality of equivalent circuits that implements a gate operation same as the first quantum gate by a second quantum gate of which a gate operation is performed by the quantum device, based on a relaxation time of a qubit to be operated by the detected first quantum gate; and converting the first quantum gate in the quantum circuit into the determined equivalent circuit.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Applicant: FUJITSU LIMITEDInventors: Masatoshi ISHII, Hirotaka OSHIMA
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Patent number: 12216430Abstract: An image forming apparatus, having a main housing, a first photosensitive drum, a second photosensitive drum, a first developing device to supply toner to the first photosensitive drum, a second developing device to supply toner to the second photosensitive drum, a first reloading device to reload the first developing device with the toner, and a second reloading device to reload the second developing device with the toner, is provided. The first reloading device has a first reloading port, which accepts the toner for reloading the first developing device. The first reloading port is openable to an outside of the main housing. The second reloading device has a second reloading port, which accepts the toner for reloading the second developing device. The second reloading port is openable to the outside of the main housing.Type: GrantFiled: December 13, 2023Date of Patent: February 4, 2025Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventors: Yasutada Kato, Shunsuke Ishii, Masatoshi Shiraki, Shougo Sato
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Patent number: 12124946Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.Type: GrantFiled: May 22, 2023Date of Patent: October 22, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Masatoshi Ishii, Takeo Yasuda
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Patent number: 12096110Abstract: There is provided with an image-processing apparatus for indicating a range, which is displayed by a device or a system comprising a display area for displaying an image, within an input image. A first obtaining unit obtains information that represents a display form of the device or the system comprising the display area. A second obtaining unit obtains input image data representing the input image. An identification unit identifies the range, which is displayed in the display area, within the input image based on the input image data and the information. An output unit outputs information that represents the identified range. A shape of the identified range depends on the display area that corresponds to at least a curved screen or a plurality of flat screens.Type: GrantFiled: July 28, 2020Date of Patent: September 17, 2024Assignee: Canon Kabushiki KaishaInventor: Masatoshi Ishii
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Publication number: 20240303941Abstract: An information processing apparatus includes one or more processors and one or more memories. The one or more processors and the one or more memories are configured to acquire play area information about a first play area indicating a movable range of a first user in a real space, set a second play area indicating a movable range of a second user in the real space, and set the second play area according to whether the first play area overlaps the set second play area.Type: ApplicationFiled: February 23, 2024Publication date: September 12, 2024Inventor: MASATOSHI ISHII
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Publication number: 20240296366Abstract: A non-transitory computer-readable recording medium stores a quantum circuit design program for causing a computer to execute processing including: detecting, from a first quantum circuit that is a quantum circuit that includes a elements and that indicates operation order on each of a qubits included in a quantum computer by arrangement of each of the elements in the quantum circuit, a first element that indicates a predetermined operation on first qubits among qubits and a second element that indicates the predetermined operation on the first qubits; and generating a second quantum circuit obtained by converting the first element of the first quantum circuit into a first equivalent circuit for ion operation that corresponds to the first qubits and converting the second element into a second equivalent circuit arranged by symmetrically moving elements of the first equivalent circuit in an arrangement direction of the first qubits.Type: ApplicationFiled: May 15, 2024Publication date: September 5, 2024Applicant: FUJITSU LIMITEDInventor: Masatoshi ISHII
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Patent number: 12063331Abstract: In an image processing apparatus, a condition for detecting a print position deviation on a print medium in a printed material is set. Based on the condition, data obtained by reading the print medium for the print position deviation is inspected. In the condition, in a case where a width of the print medium is larger than a readable width for reading the print medium, a settable range is small relative to a case where the width of the print medium is smaller than the readable width.Type: GrantFiled: December 8, 2021Date of Patent: August 13, 2024Assignee: Canon Kabushiki KaishaInventor: Masatoshi Ishii
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Publication number: 20240169234Abstract: A quantum circuit design apparatus includes: a memory; and a processor coupled to the memory and configured to: detect a first gate indicating a predetermined operation on a plurality of first quantum bits among a plurality of quantum bits included in a first quantum circuit, which includes a plurality of elements and indicates an operation order on the plurality of quantum bits by an arrangement of each of the plurality of elements, and a second gate which indicates the predetermined operation; and generate a second quantum circuit by converting the first gate into a first equivalent circuit in the first quantum circuit and converting the second gate into a second equivalent circuit in which the plurality of elements are symmetrically moved in an arrangement direction of the plurality of first quantum bit.Type: ApplicationFiled: January 12, 2024Publication date: May 23, 2024Applicant: FUJITSU LIMITEDInventor: Masatoshi ISHII
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Patent number: 11962946Abstract: There is provided with an image processing apparatus that generates a display image to be displayed in a display system including a display area. An obtaining unit obtains one input image acquired through shooting by one image capturing apparatus. A generating unit generates the display image from the input image on the basis of a correspondence between a first projection plane corresponding to the input image and a second projection plane corresponding to the display area.Type: GrantFiled: July 30, 2020Date of Patent: April 16, 2024Assignee: Canon Kabushiki KaishaInventor: Masatoshi Ishii
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Publication number: 20230393795Abstract: An image processing apparatus includes an image acquisition unit configured to acquire a first thumbnail image having a first angle of view recorded in an image file, an image generation unit configured to generate a second thumbnail image having a second angle of view different from the first angle of view, an image setting unit configured to set a thumbnail image to be displayed in a thumbnail display area depending on whether a cursor operated by a user is located in the thumbnail display area on a screen, and a display unit configured to display a thumbnail image set by the image setting unit in the thumbnail display area on the screen, wherein, in a case where a cursor is located in the thumbnail display area on the screen, the image setting unit sets the second thumbnail image as a thumbnail image to be displayed in the thumbnail display area.Type: ApplicationFiled: May 31, 2023Publication date: December 7, 2023Inventor: MASATOSHI ISHII
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Publication number: 20230385619Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Atsuya Okazaki, Masatoshi Ishii, Junka Okazawa, Kohji Hosokawa, Takayuki Osogami
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Publication number: 20230388475Abstract: The technique disclosed herein makes it possible to save a proper screenshot, i.e., images with display angles of view of an HMD, and also enable one to check a situation even outside the display angles of view at the time of saving the screenshot. When receiving a notification that a screen capture command is received from a command receiver, an image file generator acquires wide angle images from a wide angle image generator, acquires display angle-of-view information from a display image generator, sets the wide angle images as image data to be stored in a main image region of an image file, sets the acquired display angle-of-view information as data to be stored in a metadata region of the image file, generates an image file of a screenshot according to the settings, and saves the image file in an HDD.Type: ApplicationFiled: May 10, 2023Publication date: November 30, 2023Inventor: MASATOSHI ISHII
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Patent number: 11823740Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.Type: GrantFiled: December 8, 2021Date of Patent: November 21, 2023Assignee: International Business Machines CorporationInventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan, Paul Michael Solomon
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Publication number: 20230297821Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.Type: ApplicationFiled: May 22, 2023Publication date: September 21, 2023Inventors: Masatoshi Ishii, Takeo Yasuda
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Patent number: 11763139Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.Type: GrantFiled: January 19, 2018Date of Patent: September 19, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atsuya Okazaki, Masatoshi Ishii, Junka Okazawa, Kohji Hosokawa, Takayuki Osogami
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Patent number: 11741353Abstract: A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.Type: GrantFiled: December 9, 2020Date of Patent: August 29, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Masatoshi Ishii, Takeo Yasuda