Patents by Inventor Masatoshi Kato

Masatoshi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030178873
    Abstract: A cowl structure for a vehicle, which includes: a box-section cross member under a windshield of the vehicle; an extension member extending frontward from a base wall of the cross member; and a wiper bracket attached to a front wall of the cross member and the extension member. Either the base wall of the cross member or the extension member is provided with a rigidity changing part.
    Type: Application
    Filed: February 3, 2003
    Publication date: September 25, 2003
    Applicant: Nissan Motor Co., Ltd.
    Inventors: Masatoshi Kato, Yasushi Murakami
  • Patent number: 6624044
    Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: September 23, 2003
    Assignee: Denso Corporation
    Inventors: Hiroyasu Ito, Takafumi Arakawa, Masatoshi Kato
  • Patent number: 6585848
    Abstract: A mounting method for mounting an electroconductive sheet on a developer seal member for sealing a developer discharging opening provided in a developer accommodating container for accommodating a developer. The electroconductive sheet is provided with an adhesive material on one surface thereof. A separation sheet is adhered to the one surface, wherein the separation sheet is larger than the electroconductive sheet. The method includes a suction step of contacting a suction tool to the other surface of the electroconductive sheet. The suction tool is effective to suck air to attract the electroconductive sheet thereon. An exposure step separates the separation sheet from the electroconductive sheet, while the electroconductive sheet is being sucked by the attraction tool, so that the one surface of the electroconductive sheet is exposed.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 1, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Chadani, Masatoshi Kato, Toshiaki Nagashima
  • Patent number: 6573144
    Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: June 3, 2003
    Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
  • Patent number: 6540443
    Abstract: A ground-boring apparatus for boring the ground within a casing tube, which is driven into the ground by a casing tube pusher machine to prevent the surrounding soil from collapsing into a to be formed hole. The soil removed by an extensible kelly bar to be suspended by a movable crane, a boring bucket attached to the lower end of the kelly bar, a supporting frame unit to be placed on the casing tube for holding the kelly bar rotatably about its vertical axis, hydraulic motors provided on the supporting frame unit for turning the kelly bar about its vertical axis, and clamping devices for joining the supporting frame unit and the casing tube.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 1, 2003
    Assignees: Bauer Maschinen GmbH, Kato Kenki Yugen Kaisha
    Inventors: Masatoshi Kato, Shigeki Ashida, Daisuke Fujiki, Leonhard Weixler
  • Patent number: 6525066
    Abstract: A compound represented by the following Formula (I) or a pharmaceutically acceptable salt thereof: wherein R1 represents a hydrogen atom or a carboxyl-protecting group, R2 represents a hydrogen atom, a halogen atom, a lower alkyl group, a lower alkoxy group or a hydroxyl group, R3 represents a hydrogen atom, a halogen atom, a lower alkyl group, a lower alkoxy group, a lower alkylthio group, a nitro group, a cyano group, a hydroxyl group or an amino group; R4 represents a hydrogen atom, an amino-protecting group, an alkyl group or a cycloalkyl group, and R5 represents a hydrogen atom, a halogen atom, an alkyl group, an alkenyl group, a cycloalkyl group, an aryl group, an alkoxy group, an alkylthio group, a hydroxyl group, an imino group or an amino group.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: February 25, 2003
    Assignee: SATO Pharmaceutical Co., Ltd.
    Inventors: Ryoichi Fukumoto, Hiroyuki Kusakabe, Chong Chu, Hiroaki Kimura, Satoshi Yanagihara, Masatoshi Kato, Chisato Hirosawa, Seiji Ishiduka, Fusae Shizume
  • Publication number: 20020190309
    Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.
    Type: Application
    Filed: August 2, 2002
    Publication date: December 19, 2002
    Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
  • Publication number: 20020173517
    Abstract: A compound represented by the following Formula (I) or a pharmaceutically acceptable salt thereof: 1
    Type: Application
    Filed: April 18, 2002
    Publication date: November 21, 2002
    Applicant: SATO PHARMACEUTICAL CO., LTD.
    Inventors: Ryoichi Fukumoto, Hiroyuki Kusakabe, Chong Chu, Hiroaki Kimura, Satoshi Yanagihara, Masatoshi Kato, Chisato Hirosawa, Seiji Ishiduka, Fusae Shizume
  • Patent number: 6465839
    Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: October 15, 2002
    Assignee: Denso Corporation
    Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
  • Patent number: 6448139
    Abstract: A semiconductor substrate has a trench for forming a gate insulation film and a gate electrode therein, or an insulated isolation isolating a semiconductor element like a transistor from other elements. The trench is formed by anisotropic dry etching. After that, a shape of the trench is improved so that a bottom portion and an opening portion are rounded or tapered by a wet process using a mixed solution containing hydrofluoric acid and nitric acid. By modifying the shape of the trench, electrical characteristics of the trench are improved. For example, an oxide film formed in the trench has high quality, whereby a gate withstanding voltage is improved.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: September 10, 2002
    Assignee: Denso Corporation
    Inventors: Hiroyasu Ito, Takafumi Arakawa, Masatoshi Kato
  • Patent number: 6429673
    Abstract: The pneumatic cylinder is fixed on between the lower member of the upper unit and the lower member of the lower unit. As the shaft of the pneumatic cylinder extends, the upper unit starts lowering by its own weight at first. When the upper unit reaches to the point limited by the stopper, the lower unit then starts rising and the lower unit stops in a state where the shaft has extended to its full length. In this state, the probes and are in contact with the printed wiring board as applying a specified pressure to it.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: August 6, 2002
    Assignee: ITC Company Ltd.
    Inventors: Osamu Obata, Masatoshi Kato
  • Publication number: 20020064392
    Abstract: A developer container containing a developer has a developer containing unit containing a developer and a sealing member supplied between a plurality of members to prevent a leak of the developer, said sealing member being a liquid elastomer, and, in an area in which said liquid elastomer is supplied, the supply amount in end portions being larger than the supply amount in an intermediate portion.
    Type: Application
    Filed: November 23, 2001
    Publication date: May 30, 2002
    Inventors: Toshihiko Miura, Masatoshi Kato, Kanji Yokomori
  • Publication number: 20020005550
    Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+-type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.
    Type: Application
    Filed: April 6, 2001
    Publication date: January 17, 2002
    Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
  • Publication number: 20010051411
    Abstract: A semiconductor substrate has a trench for forming a gate insulation film and a gate electrode therein, or an insulated isolation isolating a semiconductor element like a transistor from other elements. The trench is formed by anisotropic dry etching. After that, a shape of the trench is improved so that a bottom portion and an opening portion are rounded or tapered by a wet process using a mixed solution containing hydrofluoric acid and nitric acid. By modifying the shape of the trench, electrical characteristics of the trench are improved. For example, an oxide film formed in the trench has high quality, whereby a gate withstanding voltage is improved.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 13, 2001
    Inventors: Hiroyasu Ito, Takafumi Arakawa, Masatoshi Kato
  • Publication number: 20010048132
    Abstract: By improving profile of impurity concentration in a channel portion of an FET or an IGBT of a trench gate type, variation of threshold value is lessened, and a destruction caused by current concentration is prevented while suppressing deterioration of cut-off characteristics. An island of a base region of p-type is formed in a semiconductor substrate of n-type by carrying out high acceleration ion implantation twice followed by annealing, so that the impurity concentration profile in a channel portion changes gradually in a depth direction. Accordingly, it is possible to lessen variation of the threshold value and to reduce pinch resistance while at the same time improving sub-threshold voltage coefficient and conductance characteristics.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 6, 2001
    Inventors: Hiroyasu Ito, Masatoshi Kato, Takafumi Arakawa
  • Publication number: 20010046762
    Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.
    Type: Application
    Filed: May 11, 2001
    Publication date: November 29, 2001
    Inventors: Hiroyasu Ito, Takafumi Arakawa, Masatoshi Kato
  • Publication number: 20010041099
    Abstract: To efficiently bore a hole of a desired diameter regardless of ground conditions of a boring site without the need of an auxiliary crane and thereby curtail processes required for boring operation, a ground-boring apparatus for boring the ground within a casing tube (2), which is driven into the ground by a casing tube pusher machine (3) to prevent the ground from collapsing into a bored hole, and for removing soil from the inside of the bored hole comprises an extensible kelly bar (10) to be suspended by a movable crane, a boring bucket (14) attached to the lower end of the kelly bar (10), a supporting frame unit (11) to be placed on the casing tube (2) for holding the kelly bar (10) rotatably about its vertical axis, hydraulic motors (116) provided on the supporting frame unit (11) for turning the kelly bar (10) about its vertical axis, and clamping devices (114) for joining the supporting frame unit (11) and the casing tube (2) to thereby ensure the rotation of the kelly bar (10) counteracting a reaction f
    Type: Application
    Filed: May 10, 2001
    Publication date: November 15, 2001
    Inventors: Masatoshi Kato, Shigeki Ashida, Daisuke Fujiki, Leonhard Weixler
  • Publication number: 20010030015
    Abstract: A mounting method for mounting an electroconductive sheet on a developer seal member for sealing a developer discharging opening provided in a developer accommodating container for accommodating a l, developer, wherein the electroconductive sheet is provided with an adhesive material on one of the surfaces thereof and a separation sheet on the one of the surface, the separation sheet being larger than the one of the surfaces of the separation sheet, the method includes an attraction step of contacting an attraction tool to the other surface of the electroconductive sheet, the attraction tool being effective to suck air to attract the electroconductive sheet thereon; an exposure step of separating the separation sheet from the electroconductive sheet while the electroconductive sheet is kept attracted by the attraction tool, so that surface of the electroconductive sheet provided with the adhesive material is exposed; and a bonding step of bonding, after the exposure step, the surface of the electroconductive
    Type: Application
    Filed: February 8, 2001
    Publication date: October 18, 2001
    Inventors: Kazuo Chadani, Masatoshi Kato, Toshiaki Nagashima
  • Patent number: 6222377
    Abstract: A probe is provided for electrically testing high-density printed circuit boards on a bed of nails test fixture. An elongated probe is provided with a fixed contact point interfacing with the PCB under test and a spring loaded probe on the opposite end of the probe barrel contact the interface between the test fixture and test equipment. A mechanism is provided which maintains the probe in precise perpendicular orientation to the X and Y planes while permitting movement of the probe along its axis in the Z plane.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 24, 2001
    Inventor: Masatoshi Kato
  • Patent number: 6130547
    Abstract: An apparatus for testing integrity of a printed circuit board is provided which employs a probe with moveable and/or fixed needle portions at its ends and a flange, probe retention boards having apertures for sliding the probe through, an interface board disposed parallel to the probe retention boards. The flange is disposed between the retention boards and the interface board. The needle portion provided away from the interface board comes in contact with the printed circuit board for testing. No socket is used in the apertures for accommodating the probe in the apertures. An assembly kit including these parts are provided for assembly by a user.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: October 10, 2000
    Inventor: Masatoshi Kato