Patents by Inventor Masatsugu Shinozaki

Masatsugu Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5471610
    Abstract: Character string retrieval method and system for deciding en bloc whether or not a plurality of search terms as designated exist in a text composed of characters expressed in the form of character codes is characterized by inclusion of a character string storage unit for storing a text, a filtering unit for fetching character codes from a text read out from the character string storage unit to thereby output only those character codes that are included in the search term, and a character string matching unit for matching en bloc to decide whether or not the aforementioned search term exists in the string of character codes outputted from the filtering unit.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: November 28, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hisamitsu Kawaguchi, Katsumi Tada, Kanji Kato, Masatsugu Shinozaki
  • Patent number: 5462442
    Abstract: In a connector having a plurality of first contact groups arranged in a predetermined pattern, conductors whose one ends are connected to the first contact groups, and a plurality of second contact groups arranged in a pattern corresponding to the pattern of the first contact groups, the conductors for connecting the first contact groups and the second contact groups cause portions of the first contact groups to be connected to the second contact groups at different positions within the above-described pattern. Accordingly, even when the contacts of the same sort of signal lines having one-to-one correspondence are allocated to the contact conductors located at the same positions within the boards for constituting the respective modules, the one-to-one correspondence can be maintained, and thus the printed-circuit boards of the modules can be commonly utilized.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: October 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Umemura, Toshihiko Ogura, Hideki Osaka, Masatsugu Shinozaki
  • Patent number: 5301294
    Abstract: An address bus control system is provided of the type in which a controller including a central processing unit is connected through an address bus and a data bus to hardware modules which control equipment to be controlled. An address space defined by an address bus includes a discrimination space for discriminating the attribute of the hardware module and a function space for allocating and clearing an address space for a function interface of the hardware module. The attribute of a hardware module connected to a connector having a corresponding address is recognized using the discrimination space. The function interface of each hardware module is assigned a space within the function space in accordance with the contents of the discrimination space in concern, or the assigned space is canceled.
    Type: Grant
    Filed: April 23, 1991
    Date of Patent: April 5, 1994
    Assignees: Hitachi Ltd., Hitachi Techno Engineering Co., Ltd.
    Inventors: Takahiro Kawai, Masatsugu Shinozaki, Hitoshi Sadamitsu, Tadashi Kyoda, Katsuya Takanashi, Hironori Uchida
  • Patent number: 4959770
    Abstract: In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit.
    Type: Grant
    Filed: May 22, 1987
    Date of Patent: September 25, 1990
    Assignees: Hitachi Ltd., Hitachi Microcomputer Engineering
    Inventors: Megumu Kondo, Shuji Kamiya, Kazuhiko Fukuoka, Masatsugu Shinozaki, Hitoshi Sadamitsu
  • Patent number: 4644563
    Abstract: For transmitting binary data at a data transmission speed of F=1/[(N+1)T] bits/second, where N represents a value selected in accordance with a given transmission speed and T represents a predetermined constant period, a transmitter station sends out a bipolar signal on a transmission line for the period T (seconds) corresponding to one of the states of the binary data independent of the data transmission speed, while no data is sent out on the transmission speed, while no data is sent out on the transmission line for the period NT (seconds) as well as for a period corresponding to the other state of the binary data. In a receiving station, the binary states of the data are discriminatively determined from the bipolar signal received through the transmission line in accordance with the data transmission speed F, the data being converted to a unipolar signal such as NRZ signal.
    Type: Grant
    Filed: June 16, 1982
    Date of Patent: February 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shiro Ohishi, Masatsugu Shinozaki
  • Patent number: 4475155
    Abstract: A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.
    Type: Grant
    Filed: November 19, 1981
    Date of Patent: October 2, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Shiro Oishi, Masatsugu Shinozaki