Patents by Inventor Masaya Sumita

Masaya Sumita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10186479
    Abstract: A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidenori Katsumura, Shinya Tokunaga, Masaya Sumita, Hiroyoshi Yoshida, Yasuhiro Sugaya, Kazuhide Uriu, Osamu Shibata
  • Publication number: 20170162490
    Abstract: A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.
    Type: Application
    Filed: February 7, 2017
    Publication date: June 8, 2017
    Inventors: HIDENORI KATSUMURA, SHINYA TOKUNAGA, MASAYA SUMITA, HIROYOSHI YOSHIDA, YASUHIRO SUGAYA, KAZUHIDE URIU, OSAMU SHIBATA
  • Patent number: 8290445
    Abstract: An electronic device includes a transmitter circuit, a receiver circuit, a first conductor, and a second conductor of a return path being a grounded line. The first conductor is surrounded by a dielectric. A plurality of resistive elements are connected in parallel between the first conductor and the second conductor. The first conductor transfers therethrough a transmission signal from the transmitter circuit. The length of the line of the first conductor is set to be greater than or equal to one half of the product between the inverse of the signal transfer rate of the first conductor and the velocity of light traveling through the dielectric. The resistive elements are provided along the line of the first conductor for every unit distance being equal to one half of the product between the signal transfer rate of the first conductor and the velocity of light traveling through the dielectric. Thus, it is possible to reduce the signal waveform distortion along the transmission line.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 16, 2012
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 8116415
    Abstract: The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN in synchronization with the reference clock CK; a frequency divider circuit for multiplying the frequency of the reference clock CK by n/m (m and n are integers equal to or more than 2 and m>n); a data signal buffer circuit for transmitting a data signal held by the transmitter flipflop circuit; and a clock buffer circuit for transmitting the output of the frequency divider circuit.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Toru Wada, Masaya Sumita
  • Patent number: 8067976
    Abstract: A semiconductor integrated circuit (1) comprises a substrate voltage control circuit (10A), a drain current adjuster (E1), a MOS device characteristic detection circuit (20), and a drain current compensator (E2). The substrate voltage control circuit (10A) has at least one substrate voltage supply MOS device (m1) for controlling the supply of the substrate voltage of the semiconductor integrated circuit (1). The drain current adjuster (E1) adjusts the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1). The MOS device characteristic detection circuit (20) has a characteristic detection device (m2) for detecting the characteristics of the substrate voltage supply MOS device (m1).
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: November 29, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 8040170
    Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: October 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 8035134
    Abstract: In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1?i?n?1) functional block and the source voltage input terminal of the NMOS transistor therein are connected bijectively with the source voltage input terminal of the PMOS transistor in the i+1th functional block and the substrate voltage input terminal of the NMOS transistor therein. In the nth functional block, the substrate voltage input terminal of the PMOS transistor and the source voltage input terminal of the NMOS transistor are connected to their voltage supply terminals, respectively.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 8030969
    Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7999603
    Abstract: Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: August 16, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaya Sumita, Shirou Sakiyama, Masayoshi Kinoshita
  • Patent number: 7969194
    Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Publication number: 20110090015
    Abstract: A semiconductor integrated circuit includes a first ring oscillator to which a stress voltage is applied; a second ring oscillator to which the stress voltage is not applied; and a phase comparator configured to receive an output of the first ring oscillator and an output of the second ring oscillator, and to compare phases of the outputs. The first ring oscillator includes a switch circuit configured to switch between a first connection state in which ring connection of the first ring oscillator is disconnected to connect a predetermined node of the second ring oscillator to a predetermined node of the first ring oscillator, and a second connection state in which connection between the first ring oscillator and the second ring oscillator is disconnected to connect the first ring oscillator in a ring.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 21, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masaya Sumita, Keiichi Fujimoto
  • Patent number: 7923982
    Abstract: A semiconductor integrated circuit is provided with a voltage level detector which detects a voltage level of a signal wire, and a transition time detector which detects a time length of a transition period during which the signal wire changes from an inactive voltage state to an active voltage state based on the voltage level detected by the voltage level detector. The voltage level detector detects the voltage level of the signal wire during the transition period.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7920002
    Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Akinori Matsumoto, Takashi Morie, Kazuaki Sogawa, Yukihiro Sasagawa, Masaya Sumita
  • Publication number: 20110063008
    Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 17, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masaya SUMITA
  • Patent number: 7906800
    Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7907438
    Abstract: In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 and 21AR2. A second holding circuit 30B is dedicated to a second functional block having one second write port section 31AW and one second read port section 31BR. When it is necessary to read data held in the first holding circuit 20A from the second read port section 31BR, for example, a data interchange operation is performed as follows. After the data of the second holding circuit 30B is latched in a latch circuit 40, the data of the first holding circuit 20A is transferred to the second holding circuit 30B, and then the data of the second holding circuit 30B latched in the latch circuit 40 is transferred to the first holding circuit 20A. Thus, the area necessary to provide a register file is significantly reduced.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7880520
    Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: February 1, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Publication number: 20110012641
    Abstract: Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masaya SUMITA
  • Publication number: 20110012656
    Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masaya SUMITA
  • Publication number: 20110010682
    Abstract: A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact.
    Type: Application
    Filed: September 10, 2010
    Publication date: January 13, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masaya SUMITA