Abstract: A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

Abstract: A semiconductor IC capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing stable operation.

Abstract: A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output data signal, the retaining circuit retains the output data signal, and the feedback circuit inputs therein the input data signal and the output data signal to thereby generate the feedback signal based on logic combinations of the input data signal and the output data signal, and an internal operation of the latch circuit is turned on/off by means of the feedback signal.

Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.

Abstract: Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of uninverted bit line and the voltage of inverted bit line are exchanged before any of all memory cells belonging to the same column is selected by a word line. With this structure, a predetermined potential difference is ensured between the complementary bit line pair at the time of an activation of a sense amplifier even if the total sum of the off-leak currents of access transistors in all the memory cells belonging to the same column is almost as large as the ON-current (drive current) of a single drive transistor.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation.

Abstract: In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 and 21AR2. A second holding circuit 30B is dedicated to a second functional block having one second write port section 31AW and one second read port section 31BR. When it is necessary to read data held in the first holding circuit 20A from the second read port section 31BR, for example, a data interchange operation is performed as follows. After the data of the second holding circuit 30B is latched in a latch circuit 40, the data of the first holding circuit 20A is transferred to the second holding circuit 30B, and then the data of the second holding circuit 30B latched in the latch circuit 40 is transferred to the first holding circuit 20A. Thus, the area necessary to provide a register file is significantly reduced.

Abstract: Each of D flip-flops (FFs) 13a to 13f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply voltage and a ground voltage is sent from a voltage generating circuit 17 to the test operation input circuit of each FF in the test operation. In this case, the amount of an output change in data in each FF is smoother than that in the case in which the supply voltage is applied. Consequently, the delay time of the data is increased. The intermediate voltage to be applied to each FF in the test operation is determined based on a feedback signal sent from a test circuit 15 for checking whether scanned-out data have an error or not.

Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.